參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 87/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
77
August 22, 2002 – Revision 1.02
11
Clock 7 disable
R/W
If bit is 0, then S_CLKOUT [7] is enabled.
If bit is 1, then S_CLKOUT [7] is disabled and driven low.
If bit is 0, then S_CLKOUT [8] is enabled.
If bit is 1, then S_CLKOUT [8] is disabled and driven low.
If bit is 0, then S_CLKOUT [9] is enabled.
If bit is 1, then S_CLKOUT [9] is disabled and driven low.
Reserved. Returns 00 when read.
12
Clock 8 disable
R/W
13
Clock 9 disable
R/W
15:14
Reserved
RO
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
16
Address Parity
Error
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
17
Posted Write
Data Parity Error
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
attempts.
18
Posted Write
Non-delivery
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
19
Target Abort
during Posted
Write
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
20
Master Abort
during Posted
Write
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
24
attempts.
21
Delayed Write
Non-delivery
R/WC
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
attempts.
22
Delayed Read –
No Data from
Target
R/WC
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
23
Delayed
Transaction
Master Timeout
R/WC
Reset to 0.
14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
1
Primary MEMR
Command Alias
Enable
R/W
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
相關(guān)PDF資料
PDF描述
PESDXL2BT Low capacitance double bidirectional ESD protection diodes in SOT23
PESDXL2UM LJT 23C 21#20 2#16 PIN RECP
PETAM1270BK300R BRAID SLEEVING 300M
PETAM1270BK50C 5V RS232 Transceiver with One Receiver Active in SHUTDOWN
PETAM1901BK200R BRAID SLEEVING 300M
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PERINCSPRT5PKM 制造商:Dialogic Corporation 功能描述:SERVICE;5PK;PERINCIDENT;HW;SUP
PER-M18 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-150/ 153/ 154/ 172/ 192/ 1722/ 1922/ 2122/ 2215 (VESA 100)
PER-M20 制造商:AAEON 制造商全稱:AAEON 功能描述:Desktop Stand For ONYX-170/ 172/ 173/ 174/ 175/ 175S/175X/ 175V/ 190/ 192/ 193/ 195/ 195S/ 195X/195V/ 1722/ 1922/ 2122/ 2217/ 2219 (VESA 100/75)
PERMARK-FB-1/2-1.50-9 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-1.50-9
PERMARK-FB-1/2-NO.21-9 制造商:TE Connectivity 功能描述:PERMARK-FB-1/2-NO.21-9
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*