參數(shù)資料
型號(hào)： PERICOMPI7C8150
廠(chǎng)商： Pericom Semiconductor Corp.
英文描述： 2-Port PCI-to-PCI Bridge
中文描述： 2端口PCI至PCI橋
文件頁(yè)數(shù)： 46/106頁(yè)
文件大?。?/td> 904K
代理商： PERICOMPI7C8150
PI7C8150
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
36
August 22, 2002 – Revision 1.02
PI7C8150 does not collapse sequential write transactions to the same address into a
single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
5.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C8150.
The following general ordering guidelines govern transactions crossing PI7C8150:
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed requests is important, the initiator should not start a second
delayed transaction until the first one has been completed. If more than one delayed
transaction is initiated, the initiator should repeat all delayed transaction requests,
using some fairness algorithm. Repeating a delayed transaction cannot be contingent
on completion of another delayed transaction. Otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect
to write transactions flowing in the other direction. PI7C8150 can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This
is true for PI7C81500 and must also be true for other bus agents. Otherwise, a
deadlock can occur.
PI7C8150 accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C8150.
5.3
ORDERING RULES
Table 6–1 shows the ordering relationships of all the transactions and refers by number to
the ordering rules that follow.
Table 6-1. Summary of Transaction Ordering
Pass
Posted
Write
Delayed
Read
Request
Yes
5
No
No
Yes
Delayed
Write
Request
Yes
5
No
No
Yes
Delayed Read
Completion
Delayed Write
Completion
Posted Write
Delayed Read Request
Delayed Write Request
Delayed Read
Completion
Delayed Write
Completion
No
1
No
2
No
4
No
3
Yes
5
Yes
Yes
No
Yes
5
Yes
Yes
No
Yes
Yes
Yes
No
No
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