
MOTOROLA
Contents
vii
CONTENTS
Paragraph
Number
Title
Page
Number
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.7
2.8
PowerPC Exception Model............................................................................2-22
MPC8260 Implementation-Specific Exception Model..................................2-23
Exception Priorities........................................................................................2-26
Memory Management........................................................................................2-26
PowerPC MMU Model..................................................................................2-27
MPC8260 Implementation-Specific MMU Features.....................................2-28
Instruction Timing..............................................................................................2-29
Differences between the MPC8260’s Core and the PowerPC 603e
Microprocessor...............................................................................................2-30
Chapter 3
Memory Map
Chapter 4
System Interface Unit (SIU)
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.2
4.2.2.3
4.2.3
4.2.4
4.2.4.1
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.1.3
4.3.1.4
4.3.1.5
4.3.1.6
4.3.1.7
4.3.2
4.3.2.1
System Configuration and Protection ..................................................................4-2
Bus Monitor .....................................................................................................4-3
Timers Clock....................................................................................................4-4
Time Counter (TMCNT)..................................................................................4-4
Periodic Interrupt Timer (PIT).........................................................................4-5
Software Watchdog Timer...............................................................................4-6
Interrupt Controller ..............................................................................................4-7
Interrupt Configuration ....................................................................................4-8
Interrupt Source Priorities................................................................................4-9
SCC, FCC, and MCC Relative Priority .....................................................4-12
PIT, TMCNT, and IRQ Relative Priority ..................................................4-12
Highest Priority Interrupt...........................................................................4-13
Masking Interrupt Sources.............................................................................4-13
Interrupt Vector Generation and Calculation.................................................4-14
Port C External Interrupts..........................................................................4-16
Programming Model ..........................................................................................4-17
Interrupt Controller Registers ........................................................................4-17
SIU Interrupt Configuration Register (SICR)............................................4-17
SIU Interrupt Priority Register (SIPRR)....................................................4-18
CPM Interrupt Priority Registers (SCPRR_H and SCPRR_L) .................4-19
SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L).....................4-21
SIU Interrupt Mask Registers (SIMR_H and SIMR_L)............................4-22
SIU Interrupt Vector Register (SIVEC).....................................................4-23
SIU External Interrupt Control Register (SIEXR).....................................4-24
System Configuration and Protection Registers ............................................4-25
Bus Configuration Register (BCR) ...........................................................4-25