
MOTOROLA
Contents
xiii
CONTENTS
Paragraph
Number
Title
Page
Number
10.4.5
10.4.5.1
10.4.6
10.4.6.1
10.4.6.2
10.4.6.3
10.4.6.4
10.4.6.5
10.4.6.6
10.4.6.7
10.4.6.8
10.4.7
10.4.8
10.4.9
10.4.10
10.4.11
10.4.12
10.4.12.1
10.4.13
10.5
10.5.1
10.5.1.1
10.5.1.2
10.5.1.3
10.5.1.4
10.5.1.5
10.5.1.6
10.5.2
10.5.3
10.5.4
10.6
10.6.1
10.6.1.1
10.6.1.2
10.6.1.3
10.6.1.4
10.6.2
10.6.3
10.6.4
10.6.4.1
10.6.4.1.1
10.6.4.1.2
10.6.4.1.3
Bank Interleaving ........................................................................................10-36
SDRAM Address Multiplexing (SDAM and BSMA).............................10-37
SDRAM Device-Specific Parameters..........................................................10-38
Precharge-to-Activate Interval.................................................................10-38
Activate to Read/Write Interval...............................................................10-39
Column Address to First Data Out—CAS Latency.................................10-40
Last Data Out to Precharge......................................................................10-40
Last Data In to Precharge—Write Recovery ...........................................10-41
Refresh Recovery Interval (RFRC)..........................................................10-41
External Address Multiplexing Signal.....................................................10-41
External Address and Command Buffers (BUFCMD)............................10-42
SDRAM Interface Timing............................................................................10-42
SDRAM Read/Write Transactions...............................................................10-46
SDRAM Mode-Set Command Timing ........................................................10-46
SDRAM Refresh..........................................................................................10-47
SDRAM Refresh Timing .............................................................................10-47
SDRAM Configuration Examples ...............................................................10-48
SDRAM Configuration Example (Page-Based Interleaving)..................10-48
SDRAM Configuration Example (Bank-Based Interleaving) .....................10-50
General-Purpose Chip-Select Machine (GPCM).............................................10-51
Timing Configuration...................................................................................10-52
Chip-Select Assertion Timing..................................................................10-53
Chip-Select and Write Enable Deassertion Timing.................................10-54
Relaxed Timing........................................................................................10-55
Output Enable (OE) Timing.....................................................................10-57
Programmable Wait State Configuration.................................................10-57
Extended Hold Time on Read Accesses..................................................10-57
External Access Termination.......................................................................10-60
Boot Chip-Select Operation.........................................................................10-61
Differences between MPC8xx’s GPCM and MPC8260’s GPCM...............10-62
User-Programmable Machines (UPMs)...........................................................10-62
Requests .......................................................................................................10-64
Memory Access Requests........................................................................10-65
UPM Refresh Timer Requests .................................................................10-65
Software Requests—run Command.........................................................10-66
Exception Requests..................................................................................10-66
Programming the UPMs...............................................................................10-66
Clock Timing ...............................................................................................10-67
The RAM Array...........................................................................................10-69
RAM Words.............................................................................................10-70
Chip-Select Signals (CxTx).................................................................10-74
Byte-Select Signals (BxTx) .................................................................10-75
General-Purpose Signals (GxTx, GOx)...............................................10-76