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MPC8260 PowerQUICC II User’s Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
33.4.3
33.5
33.5.1
33.6
33.7
33.7.1
33.7.1.1
33.7.1.2
33.8
33.9
33.10
SPI Command Register (SPCOM).................................................................33-9
SPI Parameter RAM.........................................................................................33-10
Receive/Transmit Function Code Registers (RFCR/TFCR)........................33-12
SPI Commands.................................................................................................33-12
The SPI Buffer Descriptor (BD) Table.............................................................33-13
SPI Buffer Descriptors (BDs).......................................................................33-13
SPI Receive BD (RxBD)..........................................................................33-14
SPI Transmit BD (TxBD).........................................................................33-15
SPI Master Programming Example..................................................................33-16
SPI Slave Programming Example....................................................................33-17
Handling Interrupts in the SPI..........................................................................33-18
Chapter 34
I
2
C Controller
34.1
34.2
34.3
34.3.1
34.3.2
34.3.3
34.3.4
34.4
34.4.1
34.4.2
34.4.3
34.4.4
34.4.5
34.5
34.6
34.7
34.7.1
34.7.1.1
34.7.1.2
Features...............................................................................................................34-2
I
2
C Controller Clocking and Signal Functions...................................................34-2
I
2
C Controller Transfers.....................................................................................34-3
I
2
C Master Write (Slave Read) ......................................................................34-4
I
2
C Loopback Testing ....................................................................................34-4
I
2
C Master Read (Slave Write) ......................................................................34-4
I
2
C Multi-Master Considerations...................................................................34-5
I
2
C Registers.......................................................................................................34-6
I
2
C Mode Register (I2MOD) .........................................................................34-6
I
2
C Address Register (I2ADD)......................................................................34-7
I
2
C Baud Rate Generator Register (I2BRG)..................................................34-7
I
2
C Event/Mask Registers (I2CER/I2CMR)..................................................34-8
I
2
C Command Register (I2COM)..................................................................34-8
I
2
C Parameter RAM...........................................................................................34-9
I
2
C Commands.................................................................................................34-11
The I
2
C Buffer Descriptor (BD) Table.............................................................34-12
I
2
C Buffer Descriptors (BDs).......................................................................34-12
I
2
C Receive Buffer Descriptor (RxBD)...................................................34-13
I
2
C Transmit Buffer Descriptor (TxBD)..................................................34-14
Chapter 35
Parallel I/O Ports
35.1
35.2
35.2.1
35.2.2
Features...............................................................................................................35-1
Port Registers......................................................................................................35-2
Port Open-Drain Registers (PODRA–PODRD).............................................35-2
Port Data Registers (PDATA–PDATD).........................................................35-2