
xlvi
MPC8260 PowerQUICC II User’s Manual
MOTOROLA
TABLES
Table
Number
Title
Page
Number
4-21
4-22
4-23
4-24
5-1
5-2
5-3
5-4
5-5
5-6
5-7
vi
6-1
7-1
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
9-1
9-2
9-3
9-4
9-5
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
PISCR Field Descriptions........................................................................................4-43
PITC Field Descriptions..........................................................................................4-44
PITR Field Descriptions..........................................................................................4-44
SIU Pins Multiplexing Control................................................................................4-45
Reset Causes..............................................................................................................5-1
Reset Actions for Each Reset Source ........................................................................5-2
RSR Field Descriptions .............................................................................................5-4
RMR Field Descriptions............................................................................................5-5
RSTCONF Connections in Multiple-MPC8260 Systems .........................................5-6
Configuration EPROM Addresses.............................................................................5-7
Hard Reset Configuration Word Field Descriptions .................................................5-8
Acronyms and Abbreviated Terms.........................................................................III-iii
External Signals.........................................................................................................6-3
DP[0–7] Signal Assignments...................................................................................7-15
Terminology ..............................................................................................................8-1
Transfer Type Encoding..........................................................................................8-10
Transfer Code Encoding..........................................................................................8-13
Transfer Size Signal Encoding ................................................................................8-13
Burst Ordering.........................................................................................................8-14
Aligned Data Transfers............................................................................................8-15
Unaligned Data Transfer Example (4-Byte Example).............................................8-16
Data Bus Requirements For Read Cycle.................................................................8-18
Data Bus Contents for Write Cycles........................................................................8-19
Address and Size State Calculations........................................................................8-20
Data Bus Contents for Extended Write Cycles........................................................8-21
Data Bus Requirements for Extended Read Cycles ................................................8-21
Address and Size State for Extended Transfers.......................................................8-22
Clock Default Modes.................................................................................................9-2
Clock Configuration Modes ......................................................................................9-2
Dedicated PLL Pins...................................................................................................9-7
SCCR Field Descriptions...........................................................................................9-8
SCMR Field Descriptions..........................................................................................9-9
Number of PSDVAL Assertions Needed for TA Assertion..................................10-12
60x Bus Memory Controller Registers..................................................................10-13
BRx Field Descriptions..........................................................................................10-14
ORx Field Descriptions (SDRAM Mode).............................................................10-16
ORx—GPCM Mode Field Descriptions................................................................10-18
Option Register (ORx)—UPM Mode....................................................................10-20
PSDMR Field Descriptions ...................................................................................10-21
LSDMR Field Descriptions...................................................................................10-24
Machine x Mode Registers (MxMR).....................................................................10-27
MDR Field Descriptions........................................................................................10-29
MAR Field Description .........................................................................................10-30