
MOTOROLA
Contents
xi
CONTENTS
Paragraph
Number
Title
Page
Number
8.4.3.1
8.4.3.2
8.4.3.3
8.4.3.4
8.4.3.5
8.4.3.6
8.4.3.7
8.4.3.8
8.4.4
8.4.4.1
8.4.4.2
8.4.5
8.5
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.6
8.7
8.7.1
8.7.2
8.8
Transfer Type Signal (TT[0–4]) Encoding................................................8-10
Transfer Code Signals TC[0–2].................................................................8-13
TBST and TSIZ[0–3] Signals and Size of Transfer...................................8-13
Burst Ordering During Data Transfers.......................................................8-14
Effect of Alignment on Data Transfers......................................................8-14
Effect of Port Size on Data Transfers ........................................................8-16
60x-Compatible Bus Mode—Size Calculation..........................................8-19
Extended Transfer Mode............................................................................8-20
Address Transfer Termination .......................................................................8-23
Address Retried with ARTRY...................................................................8-23
Address Tenure Timing Configuration......................................................8-25
Pipeline Control .............................................................................................8-26
Data Tenure Operations .....................................................................................8-26
Data Bus Arbitration......................................................................................8-26
Data Streaming Mode ....................................................................................8-27
Data Bus Transfers and Normal Termination................................................8-27
Effect of ARTRY Assertion on Data Transfer and Arbitration.....................8-28
Port Size Data Bus Transfers and PSDVAL Termination.............................8-28
Data Bus Termination by Assertion of TEA..................................................8-30
Memory Coherency—MEI Protocol..................................................................8-31
Processor State Signals.......................................................................................8-32
Support for the lwarx/stwcx. Instruction Pair................................................8-33
TLBISYNC Input...........................................................................................8-33
Little-Endian Mode............................................................................................8-33
Chapter 9
Clocks and Power Control
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.5
9.6
9.6.1
9.7
Clock Unit............................................................................................................9-1
Clock Configuration.............................................................................................9-2
External Clock Inputs...........................................................................................9-5
Main PLL.............................................................................................................9-5
PLL Block Diagram.........................................................................................9-5
Skew Elimination.............................................................................................9-6
Clock Dividers......................................................................................................9-6
The MPC8260’s Internal Clock Signals...............................................................9-6
General System Clocks....................................................................................9-7
PLL Pins...............................................................................................................9-7