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| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 90/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
78
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
When SyncEn = "1" during transmission, the value preset in the StartSync register is entered in the synchronization code
field of the first packet that is transmitted with ITStart. The values of the Sync register are then entered in the packets that
are sent secondly and thereafter. When transmission stop is effected with ITStop, the value of the StopSync register is
entered in the last packet that is transmitted shortly thereafter. In this manner, the respective values can automatically be
entered in the synchronization code field of the packet that is sent at first, the packet that is sent last, or the packet that is
sent in succession.
During reception, based on the value in the synchronization code field of the received isochronous packet, reception is
started with that packet when the contents coincide with those of the StartSync register. If the contents coincide with those
of the StopSync register, that packet is received first, then operation for packet reception can be stopped.
5-5
Cycle Master
To maintain isochronous operation, a Cycle Master is always required on the bus. To obtain this Cycle Master, it is neces-
sary to generate a cycle start event to be triggered by a CYCLE_TIME register that is synchronized with the 8kHz clock. This
function is incorporated in the MD8412B which, therefore, has a capability of being a Cycle Master.
To become a Cycle Master, the CycleMaster bit is set at "1" This is, however, possible only if there is an announcement that
the own node is a route. Being a Cycle Master, a cycle start packet is generated, synchronized with the cycle start event. It is
controlled by the CycleTimerEn bit.
The 8kHz frequency, being a clock for the cycle start event generated in the Cycle Master, is obtained through internal fre-
quency division from 49.152MHz of the master clock supplied from the PHY-chip, or by feeding an external 8kHz to the
CYCLEIN terminal. Therefore, selection is needed. This setting is controlled by the CycleSource bit.
5-6
32-bit CRC
The packet data transmitted from the MD8412B are attached with a 32-bit CRC at the header block and the data block, as
defined in the P1394 Draft. During reception, CRC is computed from data at the header block and the data block, in order to
make comparison with the CRC data attached in the received packet. If there is no coincidence as a result of comparison, an
announcement is given to the HdrErr bit located in the Interrupt register or the AckStatus bit of the Diagnostic Status register.
The following expression is used as the CRC polynomial:
X32 + X30 + X26 + X25 + X24 + X18 + X15 + X14 + X12 + X11 + X10
+ X9 + X6 + X5 + X4 + X3 + X + 1
5-7
Control flow
When the power supply is turned on, the MD8412B is set in the following procedures:
1)
RESET# is asserted to reset the device.
2)
Even after the reset operation has been completed, the MD8412B can perform setting in conjunction with the host. It
is, however, impossible to perform communication or communication with the PHY. First of all, the initial values of
the MD8412B (buffer capacity setting) must be set up.
3)
Upon completion of initial setting, connections are made toward the PHY in order to perform communication. This
can be realized by setting up the LinkOn bit (Control register).
4)
When LinkOn is set at "1", ommunication becomes possible with the PHY, and further setting becomes possible for,
such as, the acquisition of NodeID, communication with the transceiver, receiver, etc., and so on.
At the above-mentioned stage, initial setting can be finished at the time of power ON.
The subsequent steps for data transfer are possible according to the communication flow specified below.
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