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參數(shù)資料
| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 28/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
16
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
Bit6
RxPhyPkt
: Receive Phy Packet bit (RW -initial value: 0b)
= Phy Packet isn’t stored in the buffer.
= Phy Packet is stored in the buffer.
It is configured by this bit whether it isn’t put if received PHY control packet is put in the buffer area for the
reception.
When the PHY received PingPacket has more than 4 port, that SelfID Packet isn’t stored in the ARF buffer.
And, that PHY Control Packet isn’t stored in the ARF buffer when the invert data of the PHY Control Packet
is different.
0
1
Bit 10~8
BusyCtrl
: Busy Control bit (RW- Initial value: 000b)
000 = A Busy Acknowledge is returned according to the dual phase retry protocol only if there is no
vacancy of one packet to be received at the internal Async reception buffer.
001 = An Acknowledge is returned in BusyA status only if there is no vacancy of one packet to be received
at the internal Async reception buffer.
010 = An Acknowledge is returned in BusyB status only if there is no vacancy of one packet to be received
at the internal Async reception buffer.
011 = An Acknowledge is returned in BusyX status only if there is no vacancy of one packet to be received
at the internal Async reception buffer.
100 = A Busy Acknowledge is returned according to the dual phase retry protocol irrespective of whether
there is vacancy of one packet to be received at the internal Async reception buffer.
101 = An Acknowledge is returned in BusyA status for all packets received irrespective of whether there is
vacancy of one packet to be received at the internal Async reception buffer.
110 = An Acknowledge is returned in BusyB status for all packets received irrespective of whether there is
vacancy of one packet to be received at the internal Async reception buffer.
111 = An Acknowledge is returned in BusyX status for all packets received irrespective of whether there is
vacancy of one packet to be received at the internal Async reception buffer.
When the MD8412B node is of inbound and a busy status acknowledge is returned for the packet from the
outbound node transmitted to MD8412B, contents of that status are set in this register.
Bit 12
WritePending
: Write Request Ack-Pending bit (RW- Initial value: 1b)
= Ack-Complete is returned when reception is normal with Ack code for Write Request packet.
= Ack-Pending is returned when reception is normal with Ack code for Write Request packet.
When a Write Request packet is normally received, the Ack code generally returns Ack-Complete. If the
packet cannot be received normally, due to lack of buffer capacity or the like, Ack-Busy is returned. When this
bit is set at
"1"
the Ack code returns Ack-Pending under the condition that reception is normal. In other words,
Split Transaction of Write Request is to be executed. Upon completion of Write Request processing, the host is
required to transmit a Write Response packet. The table below shows types of Ack codes to be sent back for
each packet. Items mark by O are Ack codes.
0
1
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