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| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 18/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
6
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
Signal
Type
Pin
No. of
Pin
Contents
UWE#
I
87
1
Upper write enable: An enable signal of the upper word (16-bit) for a 32-
bit data bus. With active low of this signal, the upper 16-bit is also
asserted on the data bus.
Upper byte enable: An enable signal of the upper byte in 16-bit of the
upper/lower word for a 32-bit data bus. With active low of this signal, the
upper 8-bit is also asserted in the upper and lower words, respectively.
Data request: A request signal for DMA transfer. Asserted only for packet
and data transfer.
Data acknowledge: An acknowledge signal for DMA transfer. Asserted
only for packet and data transfer.
Interrupt signal: An interrupt signal for announcement to the host. This
signal is asserted when any factor arises in the interrupt register.
UBE#
I
85
1
DREQ
O
83
1
DACK#
I
84
1
INT#
O
81
1
RESET#
I
80
1
Reset: A system reset signal of the MD8412B.
Others
CYCLEIN
I
77
1
Isochronous cycle input: An external clock for counting the internal cycle
timer in 8KHz unit. When CycleSource bit is "1" in the control register, this
clock becomes valid.
Isochronous cycle output: A cycle clock output generated by counting the
internal cycle timer of the MD8412B.
CYCLEOUT
O
78
1
ITSTART
I
44
1
Isochronous Transmission Start Signal in ITSTART auto-Mode.
DIRECT
I
55
1
PHY I / F direct select signal: A changeover signal used to select direct or
isolation connection of I / F with PHY.
0: Isolation connection
1: Direct connection
Test Terminals
INP(2:0)
I
45, 51, 52
1
A signal for testing. In general, INP (2:0) is to be connected to the VSS.
TESTEN
I
46
1
A signal for testing. In general, TESTEN is to be connected to the VSS.
TLINK
I
47
1
A signal for testing. In general, TLINK is to be connected to the VSS.
TLINKSEP
I
49
1
A signal for testing. In general, TLINKSEP is to be connected to the VSS.
TRFUL
I
50
1
A signal for testing. In general, TRFUL is to be connected to the VSS.
TEST(1:0)
I
53, 54
1
A signal for testing. In general, TEST(1:0) is to be connected to the VSS.
Power supply
VDD
I
7, 19, 31, 39,
56, 62, 68, 79,
86, 94
3, 11, 15, 23,
27, 35, 43, 48,
59, 65, 71, 73,
76, 82, 90, 98
7
3.3V power supply.
VSS
I
32
GND
Table 2-1-2 MD8412B Terminal Table (2)
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