
MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
13
Bit 4
ResetTx
: Reset Transmitter bit (RW- Initial value: 0b)
= Normal condition
= Transmitter being reset
Transmitter is reset to set up a transmission-enabled condition. If a packet is being transmitted, that transmis-
sion is supported. When
"1"
set, and when internal initialization is completed later, this bit is automatically set at
"0"
.
0
1
Bit 5
ResetLink
: Reset Link Core bit (RW- Initial value: 0b)
= Normal condition
= Link core being reset
Link Core is reset to support all operation. When
"1"
set, and when internal initialization is completed later,
this bit is automatically set at
"0"
.
0
1
Bit 6
ResetDMA
: Reset DMA bit (RW- Initial value: 0b)
= Normal condition
= DMA control being reset
DMA control is reset to set up a condition enabling DMA transfer. DMA is required to complete transfer in
the Quadlet unit. The DMA transfer pointer in the Quadlet unit is cleared with this bit and the pointer is set in
the header position in the Quadlet unit. When
"1"
is set, and when internal initialization is completed later, this
bit is automatically set at
"0"
.
0
1
3-2-5
Asyncronous Buffer Size Set Register
Index
10h
Initial value
007F 00FFh
In this register, an assignment size is specified to assign an asynchronous area to the internal buffer having a 2KB capac-
ity. This size is specified in the Quadlet unit. Max configuration size is 511Quadlet.
Bit 8~0
ATotalSize
: Asynchronous Total Buffer bit (RW- Initial value: 0FFh)
All buffer sizes for asynchronous transmission and reception are specified in the Quadlet unit. All data (iso-
chronous also) remaining in the buffer before modification are abandoned.
Bit 24~16
ARxBufferSize
: Asynchronous Receive Buffer Size bit (RW- Initial value: 07Fh)
Buffer size for asynchronous reception is specified in the Quadlet unit. In this case, this value must always be
smaller than the one set by TotalSize. And configuration beyond 5Quadlet. If this value is changed, all data
remaining in the asynchronous transmission/reception buffer are abandoned. There is no influence in the isoch-
ronous domain.
7
6
5
4
3
2
1
0
ATotalSize
15
14
13
12
11
10
9
8
ATotalSize
23
22
21
20
19
18
17
16
ARxBufferSize
31
30
29
28
27
26
25
24
ARxBufferSize