- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄371097 > MD8412B (Electronic Theatre Controls, Inc.) LINK(IEEE 1394) PDF資料下載
參數(shù)資料
| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁(yè)數(shù)： | 15/114頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
3
1-4
Functional outlines
1-4-1
Host interface
The host interface is composed of asynchronous buses in a width of SRAM-style 8/16/32-bit. Since DMA control func-
tions are provided inside, DREQ signals can be generated according to the state of a buffer, enabling high-speed data trans-
fer.
Bus width changeover of 8/16/32 can be controlled by a signal of UWE#, UBE#, A1, or A0. It is possible to change reg-
ister and buffer access operation. All registers can be directly accessed from the host. In DMA transfer, internal buffer
selection is effected to enable gaining access to the selected buffer.
1-4-2
PHY interface
An interface is available, which enables direct connection with the PHY chip to process a physical layer according to
IEEE 1394. Either 100Mbps or 200Mbps is acceptable for the PHY chip to be connected.
In the IEEE1394 Draft, the connection mode for the PHY and LINK chips is classified to the following two kinds:
- DC connection
- AC connection
This IC supports both kinds of connections.
1-4-3
Transmitter
The transmitter reads out data from an asynchronous transmission buffer or an isochronous transmission buffer in the
MD8412B, and sends out a PHY interface packet through formatting into each packet format defined by IEEE P1394. If
the cycle master bit is
"1" and the node using the MD8412B is a route, then a cycle start packet is also sent out to indicate
the head of the isochronous cycle.
1-4-4
Receiver
The receiver receives a packet from the PHY interface and identifies if this packet is the one to be acquired by the node of
MD8412B. If it is found as an asynchronous packet, it is identified with a node address of MD8412B. If it is an isochro-
nous packet, it is identified with a preset channel number. If a packet is headed to this node, routing is effected toward the
asynchronous reception buffer or the isochronous reception buffer by writing the data therein. For a broadcast packet and
the snoop mode, no judgment is effected and data are written in their buffer.
1-4-5
Built-in buffer
The MD8412B incorporates a buffer in 512 32(bit) configuration with a capacity of 2K-byte in total. This is a temporary
buffer intended for data rate absorption between transmitter and host bus. The host performs data access to this buffer.
The MD8412B controls this buffer by dividing it into a maximum of 4 areas. Two of the divided areas are used at random
for asynchronous transmission and reception. The remaining two areas depend on isochronous modal setting. Each buffer
size is designated at the register. Status information, such as full or empty in the buffer, can be known at the host in the
divided unit.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MDC3105LT1 | RELAY/SOLENOID DRIVER SILICON MONOLITHIC CIRCUIT BLOCK |
| MEGA128CAN | Microcontroller WITH 128K BYTES OF ISP FLASH AND CAN CONTROLLER |
| MF-10KDS-R13-060 | CAP 50UF 5.5V +80-20% SUPERCAP PLANAR-MT ULTRA-LOWESR HIGH-PWR |
| MF-10KDS-R13-061 | CAPACITOR, BESTCAP 30 MILLI FARAD 5.5V CAPACITOR, BESTCAP 30 MILLI FARAD 5.5V; CAPACITANCE:30MF; VOLTAGE RATING, DC:5.5V; CAPACITOR DIELECTRIC TYPE:ELECTRONIC; SERIES:BESTCAP; TEMP, OP. MAX:70(DEGREE C); TEMP, OP. MIN:-20(DEGREE C); RoHS Compliant: Yes |
| MF-10KDS-R13-070 | CAP 60UF 5.5V +80-20% SUPERCAP THRUHOLE ULTRA-LOWESR HIGH-PWR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MD8451H-8/B | 制造商:undefined 功能描述: |
| MD845A-R2 | 制造商:Black Box Corporation 功能描述:MODEM 202 |
| MD845A-R2-W1 | 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR MD845A-R2 |
| MD845A-R2-W3 | 制造商:Black Box Corporation 功能描述:3 YEAR WARRANTY FOR MD845A-R2 |
| MD8748H | 制造商: 功能描述: 制造商:undefined 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。