參數(shù)資料
型號(hào)： MD8412B
廠商： Electronic Theatre Controls, Inc.
英文描述： LINK(IEEE 1394)
中文描述： 鏈接（1394）
文件頁(yè)數(shù)： 41/114頁(yè)
文件大?。?/td> 577K
代理商： MD8412B
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
29
3-2-19 Interrupt Register
Index
54h
Initial value
0000 0000h
By reading out data from this register, the host can know a variety of interrupt factors in MD8412B. All bits in this regis-
ter indicate with "1" an interrupt factor has arisen.
Bit 3
CmdReset
: Command Reset bit (RW- Initial value: 0b)
This bit is set at "1" when a packet is received, addressed to the reset area in the CSR space.
Bit 4
CycleLost
: Cycle Lost bit (RW- Initial value: 0b)
If the MD8412B node is not of the Cycle Master, this bit is set at "1" when a CycleStart packet is received
and the internal cycle timer is updated, but the next CycleStart packet cannot be received in 250ìec by that
cycle timer.
Bit 5
CycleDone
: Cycle Done bit (RW- Initial value: 0b)
Set at "1" when a certain isochronous cycle is over.
Bit 6
CycleStart
: Cycle Start bit (RW- Initial value: 0b)
Set at "1" when a new isochronous cycle is started.
Bit 7
CycleSeconds
: Cycle Seconds bit (RW- Initial value: 0b)
Set at "1" when a cycle timer possessed by MD8412B has counted 1 second.
Bit 8
SentRej
: Sent Reject bit (RW- Initial value: 0b)
Set at "1" when an asynchronous packet is received, but this packet cannot be completely received because of
lack of a vacant space enough to accommodate the packet capacity in the receiving buffer, and a busy Acknowl-
edge packet is returned from MD8412B to the source node.
Bit 9
HdrErr
: Header Error bit (RW- Initial value: 0b)
Set at "1" during reception of a packet, if the received packet contains an error header. In such a case, in iso-
chronous reception, data transfer to that receiving buffer is not performed and this packet is canceled.
Bit 10
TCodeErr
: TCode Error bit (RW- Initial value: 0b)
Set at "1" during transmission of a packet, if a code not supported by MD8412B is set in the TCode area of
the packet header.
7
6
5
4
3
2
1
0
CycleSeconds
CycleStart
CycleDone
CycleLost
CmdReset
15
14
13
12
11
10
9
8
PhyInt
BusReset
BusResetFin PhyRegRcvd
AckErr
TCodeErr
HdrErr
SentRej
23
22
21
20
19
18
17
16
ATxEnd
IRFRxEnd
ITF/IRF
RxEnd
ARxEnd
ITxEnd
ITFNoTx
IRFFlush
ITF/IRF
Flush
31
30
29
28
27
26
25
24
ARFFlush
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