參數(shù)資料
型號： MD8412B
廠商： Electronic Theatre Controls, Inc.
英文描述： LINK(IEEE 1394)
中文描述： 鏈接（1394）
文件頁數(shù)： 69/114頁
文件大小： 577K
代理商： MD8412B
MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
57
Figure 5-1-3 DREQ Negate Timing (WR#)
Figure 5-1-4 DREQ Negate Timing (RD#)
5-1-4
Interrupt processing
As a means of announcement to the host regarding the interrupt factor defined by the Interrupt register and the Interrupt
Mask register, the MD8412B is provided with an INT# signal. This INT# signal is asserted under the condition that logical
OR is established for the Interrupt factor not masked at the Interrupt Mask register with active low. Regarding the negate
condition, all bits are cleared to "1" by reading them out from the Interrupt register.
T
SCKC
max 4* T
SCKC+20ns
min 3* T
SCKC
SYSCLK
WR#
DREQ
T
SCKC
max 2* T
SCKC+20ns
min
T
SCKC
SYSCLK
WR#
DREQ
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