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參數(shù)資料
| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 31/114頁 |
| 文件大小： | 577K |
| 代理商： | MD8412B |
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
19
3-2-9
Phy Control Register
Index
20h
Initial value
0000 0000h
Using this register, a register in PHY chip is accessed. When reading a certain register, its register address is set in the
RegAddr register and the RdReg bit is made active. With the RdReg bit being active, a read request for the addressed reg-
ister is made to the PHY chip and the RdReg bit is then cleared. Contents of the addressed register from the PHY chip are
entered in the RegData register. The write request to the PHY register for the data in the RegData register is also made by
triggering the WrReg bit of the PHY address set in the RegAddr register.
Bit 7~0
RegData
: Register Data bit (RW- Initial value: 00h)
With a Write request, data being transferred to PHY are stored. With Read request also, data transferred from
PHY are stored. When reading out the contents of this register, contents of RegData are read out, the value
taken from PHY with the previous Read request. In other words, the value taken from the host cannot be
directly read out. To read out, a Read request must be sent to PHY.
Bit 11~8
RegAddr
: Register Address bit (RW- Initial value: 00h)
The address value of PHY being accessed is set.
Bit 12
WrReg
: Write Register bit (RW- Initial value: 0b)
= Normal condition
= Write request issued
A Write request is issued toward the PHY register. After this Write request, this bit is cleared.
0
1
Bit 13
RdReg
: Read Register bit (RW- Initial value: 0b)
= Normal condition
= Read request issued
A Read request is issued toward the PHY register. After this Read request, this bit is cleared.
0
1
Bit 14
RegRcvd
: Register Data Received bit (RW- Initial value: 0b)
= Normal condition
= Indicating that data from PHY have been stored in RegData after the issuing of Read request
After a Read request has been issued toward the PHY register, "1" set upon the storage of PHY data in Reg-
Data. Since then, "1" signal for testing.
cleared to
"0"
when reading is attempted once from this register.
0
1
7
6
5
4
3
2
1
0
RegData
15
14
13
12
11
10
9
8
RegRcvd
RdReg
WrReg
RegAddr
23
22
21
20
19
18
17
16
31
30
29
28
27
26
25
24
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