參數(shù)資料
型號: MD8412B
廠商: Electronic Theatre Controls, Inc.
英文描述: LINK(IEEE 1394)
中文描述: 鏈接(1394)
文件頁數(shù): 66/114頁
文件大?。?/td> 577K
代理商: MD8412B
MD8412B
54
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
5
Functional Description
5-1
Host interface
Control of MD8412B and transmission/reception data transfer are all conducted through host interface. Timing for host
interface signals is controlled by the respective signals of CS#, RD#, WR#, HA(6:0), and HD(31:0) for asynchronous transfer
as SRAM interface.
The internal register and the P1394 packet format are basically in the bus width of 32 bits. The MD8412B can, however,
control the bus width so that it can be connected to an MPU that has an 8-bit, 16-bit, or 32-bit data bus.
5-1-1
Register access timing
As shown in Figure 5-1-1, access to a register is effected through the SRAM-like asynchronous bus.
Figure 5-1-1 Host Access Timing
5-1-2
Host bus width
As shown in Table 5-1-1, a valid bit accessed from the host is determined by UWE#, UBE#, HA1, and HA0. Therefore,
if controlling the MD8412B with an 8-bit MPU, the bit is fixed at UWE="1" and UBE="1" and the address and data bus
are connected to HA(6:0) and HD(7:0). In this manner, direct control is possible.
For reading/writing in the byte unit with an 8-bit MPU, it is always necessary to do it in the unit of 4 bytes. For a 16-bit
MPU, this must be done in the unit of 2 words. The register access normally operates when an ordinary address is specified
UWE#
UBE#
HA1
HA0
access
Valid Host Bus
Buffer Bit Position
0
0
0
0
quadlet
31 - 0
31 - 0
1
0
0
0
word
15 - 0
31 - 16
1
0
1
0
word
15 - 0
15 - 0
1
1
0
0
byte
7 - 0
31 - 24
1
1
0
1
byte
7 - 0
23 - 16
1
1
1
0
byte
7 - 0
15 - 8
1
1
1
1
byte
7 - 0
7 - 0
Table 5-1-1 Valid Host Data Bus Accessed from the Host
HA
CS#
WR#
RD#
HD
Write Register
Read Register
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