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| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 83/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
71
Similarly, when reading out data from an ARF buffer, the reading order of 44h, 45h, 46h, and 47h must be followed. Sit-
uation is the same as for the isochronous ITF/IRF and IRF buffers.
When writing data in an ATF buffer in 16-bit width, writing for 8-bit width must be repeated 4 times. In this case, similar
process must be followed for accessing, repeating writing twice.
At first, data for 1 word are written in a 40h register. Writing is then forwarded in the order of 42h. When writing for 42h
is finished, data for one Quadlet become valid. Therefore, writing must be forwarded always in the order of 40h and 42h.
Similarly, when reading out data from an ARF buffer, it is necessary to read in the order of 44h and 46h. Situation is the
same as for the isochronous ITF/IRF and IRF buffers.
5-3-3-2
DMA access
It is necessary to designate an objective buffer for DMA access using a SelectDreq bit.
At first, procedures for writing in an ATF buffer in 8-bit width are described below.
In the first place, SelectDreq=00b is set to make ATF an object of DMA transfer and DMAWidth=00b to designate 8-bit
width transfer. When DMAC is started and DreqEn is then turned "1" a DREQ request is issued toward the DMAC and
DMA transfer is started. In this case, the first 1 Byte is stored in 32~24 bit of the ATF buffer and the second Byte is stored
in 23~16 bit. Likewise, the third Byte is stored in 15~8 bit and the 4th Byte is stored in 7~0 bit. Finally, data become valid
as 1-Quadlet data. Accordingly, the number of DMA transfers must be always a multiple of 4.
31
ARF Register
0
7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0 7 - - - - - - - - - - 0
44h
45h
46h
47h
Figure 5-3-5 Register Operation (ARF) for 8-Bit Width Soft Access
31
ATF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
40h
42h
Figure 5-3-6 Register Operation (ATF) for 16-Bit Width Soft Access
31
ARF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
44h
46h
Figure 5-3-7 Register Operation (ARF) for 16-Bit Width Soft Access
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