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參數(shù)資料
| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 79/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
67
Figure 5-2-10 PHYIFRST="0"; PHY-LINK I/F Reset Sequence in AC connection
The PHYIFRST bit is set at "1" if the PHY chip connected to this device is for the device other than the one conforming
to 1394a.
Also in this case, the LPS terminal generates an output at the low level shortly after the LPSOn bit has been set at "L" in
the register. Then, the PHY-LINK interface reset sequence is started. In 1.2μs after the fall of the LPS signal, this device
generates an output of CTL (1:0) and D (7:0) at the High-Z level if an AC connection has been made or at the low level in
the case of a DC connection.
When the LPSOn bit is set at "1" again, the LPS terminal begins to generate a clock output if an AC connection has been
made or an output at the high level in the case of a DC connection.
After the rise of the LPS signal at that time, an output of CTL (1:0) and D (7:0) is generated at the "L" level for the dura-
tion of 1SCLK within 6 cycles after the first SCLK. In the case of a DC connection, an output is generated at the "L" level.
Since then, DataPrefix
→
Idle is received from the PHY chip in order to complete the PHY-LINK interface reset sequence.
Figure 5-2-11 PHYIFRST="1"; PHY-LINK I/F Reset Sequence in AC connection
within
1.2μs
LPS
SCLK
CTL(0:1)
within
1.2μs
LPS
SCLK
CTL(0:1)
D(7:0)
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