參數(shù)資料
型號： MD8412B
廠商： Electronic Theatre Controls, Inc.
英文描述： LINK(IEEE 1394)
中文描述： 鏈接（1394）
文件頁數(shù)： 85/114頁
文件大?。?/td> 577K
代理商： MD8412B
MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
73
ATF buffer and the second Word is stored in 15~0 bit. Finally, data become valid as 1-Quadlet data. Accordingly, the num-
ber of DMA transfers must be always a multiple of 2.
Similarly, operation is the same when data are read from the ARF buffer by DMA transfer. Data are read from the upper
area of 32 bits.
5-3-4
Buffer control
Asynchronous buffer control is different from isochronous buffer control. Each control is described below.
5-3-4-1
Asynchronous buffer control
For both asynchronous transmission and reception, the host gains access to a buffer in the packet unit. Accordingly, as
described previously, the size must always be larger than one packet when specifying a packet size for transmission and
reception. Otherwise, the MD8412B cannot send out that packet in transmission phase. In reception phase, a BusyAck
code is returned.
31
ATF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
1’st word
↑
31
ATF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
2’nd word
↑
Figure 5-3-10 Register Operation (ATF) for 16-Bit Width DMA Access
31
ARF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
1’st word
↑
31
ARF Register
0
15 - - - - - - - - - - - - - - - - - - - - - 0
15 - - - - - - - - - - - - - - - - - - - - - 0
2’nd word
↑
Figure 5-3-11 Register Operation (ARF) for 16-Bit Width DMA Access
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