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參數(shù)資料
| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁(yè)數(shù)： | 78/114頁(yè) |
| 文件大小： | 577K |
| 代理商： | MD8412B |
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MD8412B
66
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
5-2-5
PHY-LINK I/F Reset Timing
The disable/enable control of the PHY-LINK interface is carried out with the MD8412B terminal and LPS.
The output control of the LPS signals is performed as described below, by the use of the LPSOn bit in the register of this
device, together with the external terminals and the DIRECT terminal.
Figure 5-2-9 LPS output waveform in AC connection
This device is provided with the two systems of PHY-LINK interface reset timing. The changeover operation for the reset
timing is effected with the PHYIFRST bit in the register.
The PHYIFRST bit is set at "0" if the PHY chip connected to this device is for the device other than the one conforming
to 1394a.
In this case, the LPS terminal generates an output at the low level shortly after the LPSOn bit has been set at "L" in the
register. Then, the PHY-LINK interface reset sequence is started. In 1.2μs after the fall of the LPS signal, this device gen-
erates an output of CTL (1:0) and D (7:0) at the High-Z level if an AC connection has been made or at the low level in the
case of a DC connection.
When the LPSOn bit is set at "1" again, the LPS terminal begins to generate a clock output if an AC connection has been
made or an output at the high level in the case of a DC connection.
After the rise of the LPS signal at that time, an output of CTL (1:0) is generated at the "L" level with the timing of the
front SCLK in order to complete the PHY-LINK interface reset sequence.
DIRECT
LPSOn
LPS output
1
0
0
1
1
1
0
0
0
0
1
Approx. 0.6 to 3.6MHz
clock (Duty 33%)
Table 5-2-10 LPS output
Symbol
Explanation
MIN
MAX
unit
T
LPSH
LPS"H" period in AC connection
0.09
0.50
μs
T
LPSL
LPS"L" period in AC connection
0.19
1.00
μs
Table 5-2-11 LPS Output Characteristics in AC Connection
T
LPSH
T
LPSL
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