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參數(shù)資料
| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 17/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
5
2
Terminal Description
2-1
Functional description for terminals
Signal
Type
Pin
No. of
Pin
Contents
PHY Interface
SCLK
I
72
1
Master clock: A 49.152MHz clock signal fed from the PHY chip. The
MD8412B employs this clock as a master clock signal. Usually connected
to this signal pin of the PHY chip.
Link request: The MD8412B uses this signal when making a request of
register access in the PHY chip and when using a serial bus. Usually
connected to this signal pin of the PHY chip.
PHY-LINK control: An interface control signal for data transmission/
reception with the PHY chip. Usually connected to this signal pin of the
PHY chip.
PHY-LINK data bus: A data bus for data transmission/reception with the
PHY chip. D(1:0) is used for packet transmission/reception at 100Mbps,
D(3:0) is used at 200Mbps, and all bits are used at 400Mbps.
Link Status: A LPS signal to PHY. Output in the following combination
available by register setting.
LREQ
O
74
1
CTL(1:0)
I/O
69, 70
2
D(7:0)
I/O
57, 58, 60, 61,
63, 64, 66, 67
8
LPS
O
75
DIRECT Input
LPSOn bit
LPS output
H
L
L
H
H
H
L
L
L
L
H
Approx. 0.6 to 3.6MHz
clock (Duty 33%)
Host Interface
HA(6:0)
I
92, 93, 95, 96,
97, 99, 100
1, 2, 4~6,
8~10, 12~14,
16~18, 20~22,
24~26, 28~30,
32~34, 36~38,
40~42
7
Host address: A host address for register selection
HD(31:0)
I/O
32
Host data bus: A data bus for register data access. In combination with
other signals, effective bit width is changeable among 31, 16, and 8 bits.
Combinations will described later.
WR#
I
89
1
Write enable: A writing signal for host data bus.
RD#
I
88
1
Read enable: A reading signal for host data bus.
CS#
I
91
1
Chip Select: chip selection signal for host data bus
Table 2-1-1 MD8412B Terminal Table (1)
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