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參數(shù)資料
| 型號： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁數(shù)： | 102/114頁 |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
90
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
5-9
Command-Reset Packet processing
When a Command-Reset packet (a packet addressed to the reset area in the CSR space) is received, the MD8412A may per-
form such a processing that the CmdReset bit is set at "1" in the Interrupt register without storing it in the buffer. In the case of
the MD8412B, however, the Command-Reset packet is received and stored in the ARF buffer, and the CmdReset bit is set at
"1" in the Interrupt register. However, if there is no vacancy in the ARF buffer, only processing is carried out for the
CmdReset Interrupt.
5-10 Bus Number for asynchronous packet transmission
For packet transmission, the MD8412B is provided with the various functions by which the bus number of the own node
defined in the IEEE1212 space is incorporated in the source area and the header area of the IEEE1394 packet format. The
incorporated value is either the value set with the BusNumber bit in the MD8412B register or "3FFh" according to the result
of selection at that time.
In order to make the set value be valid in the MD8412B register, it is necessary to set up the BusID bit of the first Quadlet at
"0b" in the asynchronous Quadlet/Block Transmit format. To make the bus number be a fixed value of "3FFh", it is necessary
for the BusID bit to be set at "1b".
If the BusID bit is set at "1b", the set value of the MD8412B register becomes invalid.
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