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參數(shù)資料
| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁(yè)數(shù)： | 68/114頁(yè) |
| 文件大?。?/td> | 577K |
| 代理商： | MD8412B |
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MD8412B
56
FUJIFUILM MICRODEVICES CO., LTD.
Ver 1.10
5-1-3
DMA transfer
The MD8412B supports the DMA transfer functions to assure the method of data transfer with the transmission/reception
buffer. The DMA mode is supported only that the DMA service request signal (DREQ) is of a level sense. Only one objec-
tive buffer for DMA transfer can be selected with the SelectDreq bit. Whether the DREQ signal should be made valid or
not is controlled by the DreqEn bit. For DreqEn="1", the DREQ signal is valid, Table 5-1-3 shows the assert/negate condi-
tions of the DREQ signal. For DreqEn="0" the DREQ signal always stays in the negate state.
When transferring the transmission data, necessary data size is defined at the external DMAC and then data transfer is
effected. Since then, DMA transfer is effected by setting DreqEn at "1" and issuing a DREQ request toward the DMAC.
When transferring the reception data to the host side, the data length is read first and its value is set at the DMAC then
execute the DMAC. Since then, DMA transfer is effected by setting DreqEn at "1" and issuing a DREQ request toward the
DMAC.
Figure 5-1-2 DMA Transfer Timing
Described below is an additional explanation about the NEGATE timing for the DMA service request signal (REQ). As
shown in Table 5-1-3, the NEGATE conditions are created when the internal buffer is for Full-1 Quadlet. When full writ-
ing is conducted by entering the WR# input, the DREQ signal is negated as shown in Fig. 5-1-2.
SelectDreq Bit Destination Buffer
DREQ Assert Condition
DREQ Negate Condition
00b
ATF
When ATF buffer is not full.
When ATF buffer is full. (ATFFull="1")
01b
ARF
When data remain in ARF buffer. When ARF buffer is full. (ARFEmpty="1")
10b
ITF/IRF
When ITF buffer is not full.
When ITF buffer is full. (ITFFull="1")
11b
IRF
When data remain in IRF buffer.
When IRF buffer is full. (IRFEmpty="1")
Table 5-1-3 DREQ Signal Assert / Negate Conditions
DREQ
DACK#
RD#
WR#
HD
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