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| 型號(hào)： | MD8412B |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LINK(IEEE 1394) |
| 中文描述： | 鏈接（1394） |
| 文件頁(yè)數(shù)： | 9/114頁(yè) |
| 文件大小： | 577K |
| 代理商： | MD8412B |
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MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
vii
Figure and Table Contents
Figure 1-3-1
MD8412B Block Diagram.......................................................................................................................................2
Figure 3-1-1
Register Address on 8-Bit Bus ................................................................................................................................7
Figure 3-1-2
Register Address on 16-Bit Bus ..............................................................................................................................7
Figure 5-1-1
Host Access Timing...............................................................................................................................................54
Figure 5-1-2
DMA Transfer Timing...........................................................................................................................................56
Figure 5-1-3
DREQ Negate Timing (WR#)...............................................................................................................................57
Figure 5-1-4
DREQ Negate Timing (RD#)................................................................................................................................57
Figure 5-2-1
Connection between MD8412B and PHY-Chip....................................................................................................58
Figure 5-2-2
Connection between MD8412B and MD8404......................................................................................................59
Figure 5-2-3
LREQ Stream.........................................................................................................................................................60
Figure 5-2-4
Status Request........................................................................................................................................................62
Figure 5-2-5
SinglePacketTransmit............................................................................................................................................63
Figure 5-2-6
Concatenated Packet Transmit ..............................................................................................................................64
Figure 5-2-7
Receive ..................................................................................................................................................................65
Figure 5-2-8
Speed Code (SP[0:7])............................................................................................................................................65
Figure 5-2-9
LPS output waveform in AC connection...............................................................................................................66
Figure 5-2-10 PHYIFRST="0"; PHY-LINK I/F Reset Sequence in AC connection...................................................................67
Figure 5-2-11 PHYIFRST="1"; PHY-LINK I/F Reset Sequence in AC connection...................................................................67
Figure 5-3-1
Buffer Assignment in Cases Other than IsoMode="011b"....................................................................................68
Figure 5-3-2
Buffer Assignment in the Case of IsoMode="011b".............................................................................................69
Figure 5-3-3
Sub-Buffer Size Assignment .................................................................................................................................70
Figure 5-3-4
Register Operation (ATF) for 8-Bit Width Soft Access........................................................................................70
Figure 5-3-5
Register Operation (ARF) for 8-Bit Width Soft Access........................................................................................71
Figure 5-3-6
Register Operation (ATF) for 16-Bit Width Soft Access......................................................................................71
Figure 5-3-7
Register Operation (ARF) for 16-Bit Width Soft Access......................................................................................71
Figure 5-3-8
Register Operation (ATF) for 8-Bit Width DMA Access.....................................................................................72
Figure 5-3-9
Register Operation (ARF) for 8-Bit Width DMA Access.....................................................................................72
Figure 5-3-10 Register Operation (ATF) for 16-Bit Width DMA Access...................................................................................73
Figure 5-3-11 Register Operation (ARF) for 16-Bit Width DMA Access...................................................................................73
Figure 5-3-12 Concept of ATF Operation....................................................................................................................................74
Figure 5-3-13 Concept of ARF Operation....................................................................................................................................75
Figure 5-7-1
ATF Transmission Flow -1....................................................................................................................................79
Figure 5-7-2
ATF Transmission Flow -2....................................................................................................................................80
Figure 5-7-3
ARF Reception Flow -1.........................................................................................................................................81
Figure 5-7-4
ARF Reception Flow -2.........................................................................................................................................82
Figure 5-7-5
ITF Transmission Flow..........................................................................................................................................84
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