參數(shù)資料
型號: MC68HC05CJ4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 96/114頁
文件大?。?/td> 361K
代理商: MC68HC05CJ4FB
GENERAL RELEASE SPECIFICATION
MOTOROLA
TIMER 1
MC68HC(7)05CJ4
11-6
Rev. 2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
11.5 Timer 1 Control Register (T1CR)
The TCR is a read/write register containing five control bits. Three bits enable
interrupts associated with the timer status register flags ICF, OCF, and TOF.
ICIE — Input Capture Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
OCE — Output Compare Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable
1 = Interrupt enabled
0 = Interrupt disabled
BITS 2:4 — Not used
Always read zero
IEDG — Input Edge
Value of input edge determines which level transition on TCAP pin will trigger
free-running counter transfer to the input capture register Reset does not affect
the IEDG bit.
1 = Positive edge
0 = Negative edge
OLVL — Output Level
Value of output level is clocked into output level register by the next successful
output compare and will appear on the TCMP pin
1 = High output
0 = Low output
Bit 7
654321
Bit 0
$0012
T1CR
Read:
ICIE
OCIE
TOIE
000
IEDG
OLVL
Write:
Reset:
000000
U
= Unimplemented
U = Unaffected
Figure 11-4. Timer 1 Control Register
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