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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 49/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
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MC68HC(7)05CJ4
MOTOROLA
Rev. 2.1
v
TABLE OF CONTENTS
Paragraph
Title
Page
SECTION 8
SERIAL COMMUNICATIONS INTERFACE
8.1
Introduction ................................................................................................... 8-1
8.2
Transmit Operation ....................................................................................... 8-1
8.3
Receive Operation ........................................................................................ 8-3
8.3.1
Receiver Front End ................................................................................. 8-3
8.3.2
Receiver Functional Operation ............................................................. 8-10
8.3.3
Idle Line Detect ..................................................................................... 8-12
8.3.4
Receiver Wakeup ................................................................................. 8-12
8.3.5
Idle Line Wakeup .................................................................................. 8-13
8.3.6
Address Mark Wakeup ......................................................................... 8-13
8.4
SCI Register Descriptions ........................................................................... 8-14
8.4.1
SCI Baud Rate Control Register ........................................................... 8-14
8.4.2
SCI Control Register 1 (SCCR1) .......................................................... 8-16
8.4.3
SCI Control Register 2 (SCCR2) .......................................................... 8-17
8.4.4
SCI Status Register (SCSR) ................................................................. 8-18
8.4.5
SCI Data Register (SCDR) ................................................................... 8-20
SECTION 9
SERIAL PERIPHERAL INTERFACE
9.1
Introduction ................................................................................................... 9-1
9.2
Signal Description ......................................................................................... 9-1
9.2.1
Master In Slave Out (MISO) ................................................................... 9-1
9.2.2
Serial Data In (MOSI) ............................................................................. 9-2
9.2.3
Serial Clock In/Out (SCK1) ..................................................................... 9-2
9.2.4
Slave Select (SS) ................................................................................... 9-3
9.3
SPI Registers ................................................................................................ 9-4
9.3.1
SPI Control Register (SPCR) ................................................................. 9-4
9.3.2
SPI Status Register (SPSR) ................................................................... 9-7
9.3.3
SPI Data Register (SPDR) ..................................................................... 9-8
SECTION 10
SLAVE-ONLY M-BUS
10.1
Introduction ................................................................................................. 10-1
10.2
Operation of SOMB and Ninth-Bit Detector ................................................ 10-1
10.2.1
After Reset ............................................................................................ 10-1
10.2.2
First Reception ..................................................................................... 10-1
10.2.3
After the First Reception ....................................................................... 10-2
10.2.4
Subsequent Receptions ....................................................................... 10-3
10.2.5
Acknowledgment .................................................................................. 10-3
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