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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 69/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MC68HC(7)05CJ4
SERIAL PERIPHERAL INTERFACE
MOTOROLA
Rev. 2.1
9-1
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SECTION 9
SERIAL PERIPHERAL INTERFACE
9.1 Introduction
The term “serial peripheral” refers to the fact that this interface requires separate
wires (signals) for data and clock. In this format, data does not contain an explicit
clock. The SPI scheme may be used to interconnect microcomputers located at a
short distance (usually within a single “black box” or on the same PC card). This
may comprise a system of one microcomputer and several slaves or may be a
system of microcomputers, each having the capability of either master or slave.
A practical system may include:
1. MISO master in slave out
2. MOSI master out slave in
3. SCK1 serial clock
4. SS(n) slave select(s)
This device also includes a programmable direction of data to select either MSB or
LSB first format.
9.2 Signal Description
The following subsections provide a description of the SPI signals.
9.2.1 Master In Slave Out (MISO)
In slave mode, MISO is the signal which is used to present data from a slave
device to the bus. The MISO pin will be placed in the high-impedance state when
ever a slave device is “not” selected (SS = 1) by the bus master. See Figure 9-2 for
more information. Four possible timing relationships may be chosen by use of the
control bits (CPOL) and (CPHA). The slave device and a master device must be
programmed to be in similar timing modes for proper data transfer.
In the master mode (control bit MSTR = 1), the function of MOSI and MISO are
inverted within the device. Therefore, the MISO pin becomes the data input pin for
a device which is in the master mode. (Also, the function of SCK1 switches from
being an input for system clock to one of outputting the system clock.)
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