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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 103/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MC68HC(7)05CJ4
TIMER 2
MOTOROLA
Rev. 2.1
12-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RTIE — Real Time Interrupt Enable
When this bit is set, a CPU interrupt request is generated when the RTIF bit is
set. Reset clears this bit.
COPE — COP Enable
When set, COPE turns on the COP. It can only be written to once after reset.
Reset clears COPE and either a 0 or a 1 can be written to it in order to lock in
the desired function. Please refer to 12.4 COP Watchdog Reset for more
information on the COP.
1 = COP Enabled
0 = COP disabled
IRQS — IRQ Select
This bit selects the type of input recognized by the IRQ interrupt input. It can only
be written to once after reset. Reset clears IRQS and either a 0 or a 1 can be
written to it in order to lock in the desired function.
1 = Negative Edge sensitive only.
0 = Negative Edge and Level Sensitive.Always read zero
RT1:RT0 — Real Time Interrupt Rate Select
These two bits select one of four taps from the Real Time Interrupt circuit. Table
12-1 shows the available interrupt rates with a 2 MHz bus clock. Reset sets
these two bits which selects the lowest periodic rate and gives the maximum
time in which to alter these bits if necessary. Care should be taken when altering
RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap
is modified during a cycle in which the counter is switching, an RTIF could be
missed or an additional one could be generated. To avoid problems, the COP
should be cleared before changing RTI taps.
Table 12-1. RTI and COP Rates at 2 MHz Bus Frequency
RT1:RT0
Ratio
RTI Rate
Minimum COP
Reset
00
E/214
8.2 ms
57.4 ms
01
E/215
16.4 ms
114.8 ms
10
E/216
32.8 ms
229.6 ms
11
E/217
65.5 ms
458.5 ms
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