
GENERAL RELEASE SPECIFICATION
MC68HC(7)05CJ4
GENERAL DESCRIPTION
MOTOROLA
Rev. 2.1
1-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
depend on the MCU operation modes and all pins are configured as single-chip
mode pins while the RESET pin is low.
1.4.3 Maskable Interrupt Request (IRQ)
This pin has a programmable option that provides two different choices of interrupt
triggering sensitivity. The options are:
1. negative edge-sensitive triggering only, or
2. both negative edge-sensitive and level-sensitive triggering.
The MCU completes the current instruction before it responds to the interrupt
request. When IRQ goes low for at least one tILIH, a logic one is latched internally
to signify an interrupt has been requested. When the MCU completes its current
instruction, the interrupt latch is tested. If the interrupt latch contains a logic one,
and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then
begins the interrupt sequence. See SECTION 4 INTERRUPTS for more
information on IRQ programming.
If the option is selected to include level-sensitive triggering, the IRQ input requires
an external resistor to VDD for “wire-OR” operation.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise
immunity.
On the MC68HC705CJ4, this pin becomes IRQ/VPP and has the added function of
providing the programming voltage for the on-board EPROM.
1.4.4 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A crystal or
an external clock signal connects to these pins providing a system clock.
1.4.5 TCAP and TCMP
These two pins are associated with the 16-bit timer (timer 1). TCAP is an input only
to the input capture system, and TCMP is an output only from the output compare
system. See SECTION 11 TIMER 1.
1.4.6 PA0 through PA7
Port A is an 8-bit bidirectional port which does not share any of its pins with other
subsystems. The port A data register is at $0000 and the data direction register
(DDRA) is at $0004. Reset does not affect the data register, but clears the data
direction register, thereby returning the port to inputs. Writing a one to a DDRA bit
sets the corresponding port bit to output mode.