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參數(shù)資料
| 型號(hào)： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 76/114頁(yè) |
| 文件大小： | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MC68HC(7)05CJ4
SERIAL PERIPHERAL INTERFACE
MOTOROLA
Rev. 2.1
9-7
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9.3.2 SPI Status Register (SPSR)
Read: anytime
Write: has no meaning or effect
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK1 cycle in a data transfer and it is cleared by
reading the SPSR register (with SPIF set) followed by an access (read or write)
to the SPI data register.
WCOL — Write Collision Status Flag
This error status flag is used to indicate that a serial transfer was in progress
when the MCU tried to write new data into the SPDR data register. The MCU
write is disabled to avoid writing over the data being transmitted. No interrupt is
generated because the error status flag can be read upon completion of the
transfer that was in progress at the time of the error. This flag is automatically
cleared by a read of the SPSR (with WCOL set) followed by an access (read or
write) to the SPDR register.
MODF — SPI Mode Error Interrupt Status Flag
This bit is set automatically by SPI hardware if the MSTR control bit is set to one
and the slave select input pin becomes zero. This condition is not permitted in
normal operation. This flag is automatically cleared by a read of the SPSR (with
MODF set) followed by a write to the SPCR register.
Bit 7
654321
Bit 0
$000D
SPSR
Read:
SPIF
WCOL
0
MODF
0000
Write:
Reset:
00000000
= Unimplemented
Figure 9-3. SPI Status Register
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05CT4FB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
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| MC68HC05E0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
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