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參數(shù)資料
| 型號(hào)： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁(yè)數(shù)： | 48/114頁(yè) |
| 文件大小： | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
SERIAL COMMUNICATIONS INTERFACE
MC68HC(7)05CJ4
8-2
Rev. 2.1
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start, seven data, parity, two stop bits
w/ odd, even, mark, or space parity
start, eight data, address/control, one stop bit
where address/control bit identifies special command words
When the transmit logic is enabled by writing a one to the TE control bit in the
SCCR2 register, a check is made to determine whether or not the transmit serial
shift register is empty. If it was empty (indicated by TC = 1) a preamble word of all
ones and no start bit is transmitted and normal data transmission begins. If the
shifter was not empty (TC = 0) then normal shifting continues until the current word
is shifted out including the stop bit and then a preamble is transmitted and normal
data transmission continues.
Data to be transmitted originates from the CPU and enters the serial transmit logic
when it is written to the data register (SCDR). If 9-bit data is to be transmitted, the
T8 bit should be initialized before writing to the SCDR. Writes to the SCDR register
access the write-only TDR and reads access the read-only RDR. Before writing to
the TDR, the program should read the SCSR status register. If the TDRE bit in
SCSR is clear, useful data is in the TDR and writes to TDR would erroneously
overwrite this information. If the TDRE bit is set it indicates that the TDR is empty
and a subsequent write to TDR will fill the TDR and automatically clear TDRE. As
soon as the data in the serial shifter has finished shifting out a check is made to
see if there is a new byte of data in the TDR. If TDRE = 0, then data is transferred
from the TDR to the transmit shifter and TDRE becomes set automatically
(optionally causing an interrupt). This transfer from TDR to the shifter is
synchronized with the baud rate clock. If TDRE = 1 when the shifter becomes
available and there is no preamble pending, then an idle condition will be entered
in which the TXD pin will remain high.
Messages may be separated by a serial preamble of 10 (11 if nine data bit format
is specified) bit times of marks (ones). To force this separation preamble with
minimum idle line time the following sequence is used:
1. Write last byte of first message to TDR.
2. Wait for TDRE to go high, indicating the last byte has been transferred to the
shifter.
3. Clear Transmit Enable (TE) and then set TE back to one. This queues a
preamble to immediately follow the transmission of the last character of the
first message (including stop bit).
4. Write first byte of second message to TDR.
In this sequence, if the first byte of the second message is not transferred to the
TDR prior to the finish of the preamble transmission, then the transmit data line will
simply mark idle until the TDR is finally written. Also, if the last byte of the first
message finishes shifting out (including stop bit) and TE is clear then the TC bit will
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