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| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 81/114頁 |
| 文件大小： | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
SLAVE-ONLY M-BUS
MC68HC(7)05CJ4
10-4
Rev. 2.1
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10.3 Slave M-Bus Control Register (MBCR)
SMIE — Slave M-Bus Interrupt Enable
When set, this bit enables the SOMB interrupt. There is only one source of
interrupt which is from the SMF bit. If SMIE is set when SMF is set, an interrupt
request is generated to the CPU. This bit is readable and writable and is cleared
by reset.
SME — Slave M-Bus Enable
When set, this bit enables the SOMB. When clear, the circuit is disabled and all
other status and control bits are cleared. If SME is cleared during a
transmission, the transmission is aborted and all circuits are reset. This bit is
readable and writable and is cleared by reset.
T/R — Transmit/Receive
When set, the SOMB is configured to transmit data. Upon reception of the SCL
from the master, the data in the shift register is transmitted out MSB first. After
the eighth clock pulse is received the ninth-bit detector is enabled. The SDA line
is not driven low in this case, but following the ninth clock bit the SCL line is and
SMF is set (an interrupt is generated if SMIE is set). The purpose of stretching
the clock is to allow the device to complete its service routine. The user must
release the SCL line to allow additional transmissions.
This bit is readable and writable and is cleared by reset.
NOACK — No Acknowledge
This bit, when set, will disable the acknowledge for the following transmissions.
This bit is used in multiple byte data transmission to terminate further
transmissions when invalid data was sent from the master. The master, with no
acknowledge being sent, will abort the transmission. This bit is readable and
writable, and is cleared by reset.
Bit 7
654321
Bit 0
$001D
MBCR
Read:
SMIE
SME
T/R
NOACK
000
0/1
Write:
CLKR
Reset:
0000000
0/1
= Unimplemented
Figure 10-1. M-Bus Control Register
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