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參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 105/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
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GENERAL RELEASE SPECIFICATION
MOTOROLA
TIMER 2
MC68HC(7)05CJ4
12-6
Rev. 2.1
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12.4 COP Watchdog Reset
The COP watchdog timer function is implemented on this device by using the
output of the RTI circuit and further dividing it by eight. The minimum COP reset
rates are listed in Table 12-1. If the COP circuit times out, an internal reset is
generated and the normal reset vector is fetched. Preventing a COP time-out is
done by writing a zero to bit 0 of address $1FF0. When the COP is cleared, only
the final divide by eight stage (output of the RTI) is cleared.
12.5 Timer 2 Counter Register (T2CR)
The timer 2 counter register is a read-only register which contains the current value
of the 8-bit ripple counter at the beginning of the timer chain. This counter is
clocked at E divided by 4 and can be used for various functions including a
software input capture. Extended time periods can be attained using the TOF
function to increment a temporary RAM storage location thereby simulating a 16-bit
(or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released which again
clears the counter chain and allows the device to come out of reset. At this point,
if RESET is not asserted, the timer will start counting up from zero and normal
device operation will begin. When RESET is asserted anytime during operation
(other than POR), the counter chain will be cleared.
12.6 Timer 2 During Wait Mode
The CPU clock halts during the wait mode, but the timer remains active. If
interrupts are enabled, a timer interrupt will cause the processor to exit the WAIT
mode.
12.7 Timer 2 During Stop Mode
The timer is cleared when going into stop mode. When stop is exited by an external
interrupt or an external RESET, the internal oscillator will resume, followed by a
4064 internal processor oscillator stabilization delay. The timer is then cleared and
operation resumes.
Bit 7
654321
Bit 0
$0009
T2CR
Read:
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
Write:
Unaffected by Reset
Figure 12-3. Timer 2 Counter Register
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