- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45219 > MC68HC05CJ4FB (MOTOROLA INC) 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號： | MC68HC05CJ4FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 84/114頁 |
| 文件大?。?/td> | 361K |
| 代理商： | MC68HC05CJ4FB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁當前第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁
GENERAL RELEASE SPECIFICATION
MOTOROLA
SLAVE-ONLY M-BUS
MC68HC(7)05CJ4
10-6
Rev. 2.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
10.4 Slave M-Bus Status Register (MBSR)
SMF — Slave M-Bus Flag
This bit is set after the ninth clock of a valid transmission. A valid transmission
can be either a reception of a valid address following a start condition or
transmission/reception of data after the a valid address is recognized. If SMIE is
also set, an interrupt will be generated. This bit is cleared by first reading the
MBSR with SMF set, followed by reading or writing the M-bus address/data
register. SMF is also cleared when SME is cleared or by reset.
STDF — Start Detect Flag
This bit is set when a start condition is detected. It is provided as a means for
the user to distinguish between an address and a data transmission. No
interrupt is associated with this bit. Clearing STDF is done by first reading the
MBSR with STDF set, followed by reading or writing the M-bus address/data
register. STDF is also cleared when SME is cleared or by reset.
MACK — Master Acknowledge
This bit shows the status to the acknowledge during the master read (slave
write) operation. A Master ACKnowledge happens during the ninth-bit of a slave
transmission, when the slave releases the SDA line and the master holds it low.
When an acknowledge is sent by the master, MACK will be set (logic one): If the
master does not return any acknowledge, MACK will be cleared. This provides
a mean to detect if a master is signalling an end of transmission to the slave. No
interrupt is associated with this bit. Clearing MACK is done by first reading the
MBSR with MACK set, followed by reading or writing the M-bus data register.
MACK is also cleared when SME is cleared or by reset
NOTE
The other bits in this register (0–4) are not implemented and always
read as zero.
Bit 7
654321
Bit 0
$001E
MBSR
Read:
SMF
STDF
MACK
00000
Write:
Reset:
00000000
= Unimplemented
Figure 10-2. M-Bus Status Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC05CL48 | 8-BIT, MROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| MC68HC705CL48 | 8-BIT, OTPROM, 1.802 MHz, MICROCONTROLLER, PQFP112 |
| MC68HC05CT4FN | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC05CT4FB | 8-BIT, MROM, 2.048 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC05E16CB | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC05CT4FB | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05CT4FN | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:General Release Specification |
| MC68HC05D9 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-bit microcomputer with PWM outputs and LED drive |
| MC68HC05E0 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit |
| MC68HC05E0FN | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。