參數(shù)資料
型號(hào): MC68HC05CJ4FB
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP44
封裝: QFP-44
文件頁數(shù): 67/114頁
文件大?。?/td> 361K
代理商: MC68HC05CJ4FB
GENERAL RELEASE SPECIFICATION
MC68HC(7)05CJ4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
Rev. 2.1
8-19
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IDLE — Idle Line Detected Flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of
10/11 consecutive ones). This bit will not be set by the idle line condition when
the RWU bit is set. Once cleared, IDLE will not be set again until after RDRF has
been set (until after the line has been active and becomes idle again).
OR — Over-Run Error Flag
This bit is set when a new byte is ready to be transferred from the receiver shift
register to the receiver data register and the receive data register is already full
(RDRF bit is set). Data transfer is inhibited until this bit is cleared.
NF — Noise Error Flag
This bit is set if there is noise on a “valid” start bit, any of the data bits, or on the
stop bit. The NF bit is set during the same cycle as the RDRF bit but does not
get set in the case of an over run (OR).
FE — Framing Error Flag
This bit is set when the word boundaries in the bit stream are not synchronized
with the receiver bit counter (generated by the reception of a logic zero bit where
a stop bit was expected). The FE bit reflects the status of the byte in the receive
data register and the transfer from the receive shifter to the receive data register
is inhibited in the case of over run. The FE bit is set during the same cycle as
the RDRF bit but does not get set in the case of an over run (OR). The framing
error flag inhibits further transfer of data into the RDR until it is cleared.
PF — Parity Error Flag
This bit is set when the received data’s parity does not match its parity bit. This
feature is active only when parity is enabled. The type of parity tested for is
determined by the PT (parity type) bit in SCCR1.
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