參數(shù)資料
型號(hào)： K4N56163QF-GC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit gDDR2 SDRAM
中文描述： 片256Mbit GDDR2 SDRAM的
文件頁數(shù)： 35/73頁
文件大?。?/td> 1262K
代理商： K4N56163QF-GC
- 35 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock.
The bank addresses BA0 and BA1 are used to select the desired bank. The row address A0 through A12 is used to deter-
mine which row to activate in the selected bank. The Bank Activate command must be applied before any Read or Write
operation can be executed. Immediately after the bank active command, the gDDR2 SDRAM can accept a read or write
command on the following clock cycle. If a R/W command is issued to a bank that has not satisfied the tRCDmin specifica-
tion, then additive latency must be programmed into the device to delay when the R/W command is internally issued to the
device. The additive latency value must be chosen to assure tRCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 are
supported. Once a bank has been activated it must be precharged before another Bank Activate command can be applied
to the same bank. The bank active and precharge times are defined as tRAS and tRP, respectively. The minimum time
interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the
device (t
RC
). The minimum time interval between Bank Activate commands is t
RRD
.
Bank Activate Command Cycle: tRCD = 3, AL = 2, tRP = 3, tRRD = 2, tCCD = 2
ADDRESS
CK / CK
T0
T2
T1
T3
Tn
Tn+1
Tn+2
Tn+3
COMMAND
Bank A
Row Addr.
Bank A
Activate
Bank A
Col. Addr.
CAS-CAS delay time (
t
CCD
)
. . . . . . . . . .
. . . . . . . .Bank A
. . . . . . . Bank A
Internal RAS-CAS delay (>=
t
RCDmin
)
: “H” or “L”
RAS Cycle time (
>= t
RC
)
additive latency delay (
AL
)
Read A
Post CAS
Bank B
Row Addr.
Bank B
Activate
Bank B
Col. Addr.
Read B
Post CAS
Addr.
Precharge
Bank B
Addr.
Bank B
Precharge
Bank A
Row Addr.
Active
Bank A
RAS - RAS delay time (
>= t
RRD
)
Read Begins
RCD =1
Bank Active
(>= t
RAS
)
Bank Precharge time (
>= t
RP
)
相關(guān)PDF資料
PDF描述
K4N56163QF-GC25 256Mbit gDDR2 SDRAM
K4N56163QF-GC30 256Mbit gDDR2 SDRAM
K4N56163QF-GC37 256Mbit gDDR2 SDRAM
K4PE68A Transient Voltage Suppressor Diodes
K4R271669A 256K x 16/18 bit x 2*16 Dependent Banks Direct RDRAMTM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K4N56163QF-GC25 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM
K4N56163QF-GC30 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM
K4N56163QF-GC37 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM
K4N56163QG-ZC2A 制造商:Samsung Semiconductor 功能描述:
K4P24V3 制造商:AROMAT 功能描述:REPLAY 700 OHM
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