參數(shù)資料
型號(hào)： K4N56163QF-GC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit gDDR2 SDRAM
中文描述： 片256Mbit GDDR2 SDRAM的
文件頁(yè)數(shù)： 18/73頁(yè)
文件大?。?/td> 1262K
代理商： K4N56163QF-GC
- 18 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
18. tIS and tIH (input setup and hold) derating
1) Input waveform timing is referenced from the input signal crossing at the V
IH
(AC) level for a rising signal and V
IL
(AC) for a
falling signal applied to the device under test.
2) Input waveform timing is referenced from the input signal crossing at the V
IH
(DC) level for a rising
signal and V
IL
(DC) for a falling signal applied to the device under test
19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system
performance (bus turnaround) will degrade accordingly.
20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the
half period jitter ( tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
21. tQH = tHP – tQHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH, tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which
are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
22. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
23. tDAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the application clock period. nWR
refers to the tWR parameter stored in the MRS.
Example: For gDDR533 at t CK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks =4 +(4)clocks=8clocks.
tIS
V
DDQ
V
IH
(AC) min
V
IH
(DC) min
V
REF
V
IL
(DC) max
V
IL
(AC) max
V
SS
CK
CK
tIH
tIS
tIH
<Input setup/hold timing>
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K4N56163QF-GC25 制造商:SAMSUNG 制造商全稱(chēng):Samsung semiconductor 功能描述:256Mbit gDDR2 SDRAM
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