參數(shù)資料
型號(hào)： K4N56163QF-GC
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit gDDR2 SDRAM
中文描述： 片256Mbit GDDR2 SDRAM的
文件頁(yè)數(shù)： 27/73頁(yè)
文件大小： 1262K
代理商： K4N56163QF-GC
- 27 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
EMRS(2) Programming
*1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be pro-
grammed to 0 when setting the mode register during initialization.
.
*2 : If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will
be loast if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh com-
mand is issued. PASR is supported from the device of 90nm technology(512Mb C-die, 256Mb G-die, 1Gb A-die).
*1 : All bits in EMRS(3) except BA0 and BA1 are reserved for future use and must be programmed to 0 when setting the
mode register during initialization.
Address Field
Extended Mode Register(2)
BA1
0
0
1
1
BA0
0
1
0
1
MRS mode
MRS
EMRS(1)
EMRS(2)
EMRS(3): Reserved
A7
1
0
High Temperature Self-Refresh Rate Enable
Enable
Disable
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Partial Array Self Refresh for 4 Banks
Full array
Half Array(BA[1:0]=00&01)
Quarter Array(BA[1:0]=00)
Not defined
3/4 array(BA[1:0]=01, 10&11)
Half array(BA[1:0]=10&11)
Quarter array(BA[1:0]=11)
Not defined
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Partial Array Self Refresh for 8 Banks
Full array
Half Array(BA[2:0]=000,001,010,&011)
Quarter Array(BA[2:0]=000&001)
1/8th array(BA[2:0]=000)
3/4 array(BA[2:0]=010,011,100,101,110,&111)
Half array(BA[2:0]=100,101,110,&111)
Quarter array(BA[2:0]=110&111)
1/8th array(BA[2:0]=111)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
0
*1
0
*1
SRF
0
*1
PSAR
*2
EMRS(3) Programming: Reserved
*
1
Address Field
Extended Mode Register(3)
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
1
0
*1
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