
Preliminary
Datasheet
5
80960VH
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Related Documentation.........................................................................................7
80960VH Instruction Set .....................................................................................14
Signal Type Definition .........................................................................................15
Signal Descriptions..............................................................................................16
Power Requirement, Processor Control and Test Signal Descriptions...............19
Interrupt Unit Signal Descriptions........................................................................20
PCI Signal Descriptions.......................................................................................21
Memory Controller Signal Descriptions...............................................................22
DMA, I
2
C Units Signal Descriptions ....................................................................24
Clock Related Signals .........................................................................................24
PBGA 324 Package Dimensions.........................................................................26
324-Plastic Ball Grid Array Ballout — In Ball Order ............................................27
324-Plastic Ball Grid Array Ballout — In Signal Order ........................................30
324-Lead PBGA Package Thermal Characteristics ............................................34
Absolute Maximum Ratings.................................................................................35
Operating Conditions...........................................................................................35
V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)...............36
DC Characteristics ..............................................................................................37
I
CC
Characteristics ..............................................................................................38
Input Clock Timings.............................................................................................39
Synchronous Output Timings..............................................................................39
Synchronous Input Timings.................................................................................40
Relative Output Timings......................................................................................41
Fast Page Mode Non-interleaved DRAM Output Timings...................................41
Fast Page Mode Interleaved DRAM Output Timings ..........................................41
EDO DRAM Output Timings................................................................................42
SRAM/ROM Output Timings ...............................................................................42
Boundary Scan Test Signal Timings ...................................................................43
I2C Interface Signal Timings ...............................................................................44
Processor Device ID Register - PDIDR..............................................................63