
80960VH
20
Preliminary Datasheet
TDO
O
R(Q)
H(Q)
P(Q)
TEST DATA OUTPUT
is the serial output signal for JTAG. TDO is driven on
the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the
Test Access Port. At other times, TDO floats.
TMS
I
S(L)
TEST MODE SELECT
is sampled at the rising edge of TCK to select the
operation of the test logic for IEEE 1149.1 Boundary Scan testing. This
signal has a weak internal pullup to ensure normal operation.
TRST#
I
A(L)
TEST RESET
asynchronously resets the Test Access Port (TAP) controller
function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the
Boundary Scan feature, connect a pulldown resistor (1.5 K
) between this
signal and V
. When TAP is not used, this signal must be connected to
V
; however, no resistor is required. The signal has a weak internal pullup
which must be overcome during reset to ensure normal operation.
NOTE:
The system must ensure that TRST# is asserted after power-up to
put the TAP controller in a known state. Failure to do so may
cause improper processor operation.
LCDINIT#
I
LCD INITIALIZATION
is a static signal used to initialize the internal logic of
the LCD960 debugger. This signal has an internal pullup for normal
operation.
V
CC
–
POWER
. Connect to a 3.3 Volt power board plane.
V
CC5
REF
–
5 VOLT REFERENCE VOLTAGE.
Input is the reference voltage for the
5 V-tolerant I/O buffers. Connect this signal to +5 V for use with signals
which exceed 3.3 V. When all inputs are from 3.3 V components, connect
this signal to 3.3 V.
V
SS
–
GROUND.
Connect to a V
SS
board plane.
N.C.
–
NO CONNECT
. Do not make electrical connections to these balls.
VCCPLL2:1
I
PLL POWER
. For external connection to a 3.3 V V
board plane. Power
to PLLs requires external filtering. See Section 4.2, VCCPLL Pin
Requirements.
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION