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參數(shù)資料
| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 22/64頁 |
| 文件大小： | 851K |
| 代理商： | I960 VH |
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80960VH
22
Preliminary Datasheet
P_LOCK#
I
S(L)
PRIMARY PCI BUS LOCK
indicates an atomic operation that may require
multiple transactions to complete.
P_PAR
I/O
K(Q)
R(Z)
PRIMARY PCI BUS PARITY
. This signal ensures even parity across
P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal.
P_PERR#
I/O
R(Z)
PRIMARY PCI BUS PARITY ERROR
is used for reporting data parity errors
during all PCI transactions except a special cycle.
P_REQ#
O
K(Q)
R(Z)
PRIMARY PCI BUS REQUEST
indicates to the arbiter that this agent desires
use of the bus. This is a point to point signal.
P_RST#
I
A(L)
PRIMARY RESET
brings 80960VH to a consistent state. When P_RST# is
asserted:
PCI output signals are driven to a known consistent state.
PCI bus interface output signals are three-stated.
open drain signals such as P_SERR# are floated.
S_RST# asserts.
P_RST# may be asynchronous to P_CLK when asserted or deasserted.
Although asynchronous, deassertion must be guaranteed to be a clean,
bounce-free edge.
P_SERR#
I/O
OD
R(Z)
PRIMARY PCI BUS SYSTEM ERROR
reports address and data parity errors
on the special cycle command, or any other system error where the result
would be catastrophic.
P_STOP#
I/O
R(Z)
PRIMARY PCI BUS STOP
indicates that the current target is requesting the
master to stop the current transaction on the primary PCI bus.
P_TRDY#
I/O
R(Z)
PRIMARY PCI BUS TARGET READY
indicates the target agent's (selected
device's) ability to complete the current data phase of the transaction.
Table 7. PCI Signal Descriptions (Sheet 2 of 2)
NAME
TYPE
DESCRIPTION
1
NOTE:
1.
PCI signal functions are summarized in this data sheet; refer to the
PCI Local Bus Specification, revision 2.2
for
a more complete definition.
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