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參數(shù)資料
| 型號(hào)： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 851K |
| 代理商： | I960 VH |
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80960VH
12
Preliminary Datasheet
The processor also has built-in debug capabilities. Via software, the 80960VH may be configured
to detect as many as seven different trace event types. Alternatively,
mark
and
fmark
instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.2.5
On-Chip Cache and Data RAM
External memory subsystems often impose substantial wait state penalties. The 80960VH
integrates considerable storage resources on-chip to decouple CPU execution from the external bus
by including a 16 Kbyte instruction cache, a 4 Kbyte data cache and 1 Kbyte data RAM.
2.2.6
Local Register Cache
The 80960VH rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.
2.2.7
Test Features
The 80960VH incorporates numerous features that enhance the user’s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960VH provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan
mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960VH to
electrically “remove” itself from a circuit board. This mode allows system-level testing where a
remote tester can exercise the processor system.
The test logic does not interfere with component or system behavior and ensures that components
function correctly, and also the connections between various components are correct.
The JTAG Boundary Scan feature is an alternative to conventional “bed-of-nails” testing. It can
examine connections that might otherwise be inaccessible to a test system.
2.2.8
Memory-Mapped Control Registers
The 80960VH is compliant with 80960 family architecture and has the added advantage of
memory-mapped, internal control registers not found on the 80960Kx, Sx or Cx processors. This
feature provides software an interface to easily read and modify internal control registers.
Each memory-mapped, 32-bit register is accessed via regular memory-format instructions. The
processor ensures that these accesses do not generate external bus cycles.
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