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| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 15/64頁 |
| 文件大小： | 851K |
| 代理商： | I960 VH |
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80960VH
Preliminary
Datasheet
15
3.0
Package Information
3.1
Package Introduction
The 80960VH is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array
package with five rows of ball connections in the outer area of the package. See
Figure , (pg. 26)
.
Section 3.1.1, Functional Signal Definitions
describes signal function.
Section 3.1.2, 324-Lead
PBGA Package
defines the signal and ball locations.
3.1.1
Functional Signal Definitions
Table 3
presents the legend for interpreting the Type Field in the following tables.
Table 4
defines
signals associated with the bus interface.
Table 5
defines signals associated with basic control and
test functions.
Table 6
defines signals associated with the Interrupt Unit.
Table 7
defines PCI
signals.
Table 8
defines Memory Controller signals.
Table 9
defines DMA, and I
2
C signals.
Table
10
defines clock signals.
Table 3. Signal Type Definition
Symbol
Description
I
Input signal only.
O
Output signal only.
I/O
Signal can be either an input or output.
OD
Open Drain signal.
–
Signal must be connected as described.
S (...)
Synchronous. Inputs must meet setup and hold times relative to P_CLK.
S(E) Edge sensitive input
S(L) Level sensitive input
A (...)
Asynchronous. Inputs may be asynchronous relative to P_CLK.
A(E) Edge sensitive input
A(L) Level sensitive input
R (...)
While the P_RST# signal is asserted, the signal:
R(1) is driven to V
CC
R(0) is driven to V
SS
R(Q) is a valid output
R(Z) Floats
R(H) is pulled up to V
R(X) is driven to an unknown state
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