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參數(shù)資料
| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 37/64頁 |
| 文件大?。?/td> | 851K |
| 代理商： | I960 VH |
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80960VH
Preliminary
Datasheet
37
This resistor is not necessary in systems that can guarantee the V
DIFF
specification.
In 3.3 V-only systems and systems that drive 80960VH pins from 3.3 V logic, connect the V
CC5
pin directly to the 3.3 V V
CC
plane.
4.2
V
CCPLL
Pin Requirements
To reduce clock skew on the i960 Jx processor, the V
CCPLL
pin for the Phase Lock Loop (PLL)
circuit is isolated on the pinout. The lowpass filter, as shown in Figure 7., reduces noise-induced
clock jitter and its effects on timing relationships in system designs. The 4.7 μF capacitor must be
(low ESR solid tantalum), the 0.01 μF capacitor must be of the type X7R and the node connecting
V
CCPLL
must be as short as possible.
Figure 6. V
CC5
Current-Limiting Resistor
+5 V (±0.25 V)
V
CC5
Pin
100
(±5%, 0.5 W)
Table 17. V
DIFF
Specification for Dual Power Supply Requirements (3.3 V, 5 V)
Symbol
Parameter
Min
Max
Units
Notes
V
DIFF
V
-V
Difference
2.25
V
V
input should not exceed V
by more than 2.25 V
during power-up and power-down, or during steady-state
operation.
Figure 7. V
CCPLL
Lowpass Filter
10
, 5%, 1/8W
V
CC
(Board Plane)
V
(On i960
Jx processors)
F_CA078A
0.01μF
4.7μF
+
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