參數(shù)資料
型號(hào)： i960 VH
廠商： Intel Corp.
英文描述： Embedded-PCI Processor(嵌入式PCI處理器)
中文描述： 嵌入式PCI處理器（嵌入式處理器的PCI）
文件頁數(shù)： 42/64頁
文件大小： 851K
代理商： I960 VH
80960VH
42
Preliminary Datasheet
4.4.1
Relative Output Timings
4.4.2
Memory Controller Relative Output Timings
Table 23. Relative Output Timings
Symbol
Parameter
Min
Max
Units
Notes
T
LXL
ALE Width
0.5T
C
-3
ns
(1,2,4)
T
LXA
Address Hold from ALE Inactive
0.5T
C
-1
ns
Equal Loading (1,2,4)
T
DXD
DT/R# Valid to DEN# Active
0.5T
C
-3
ns
Equal Loading (1,3,4)
NOTES:
1. Guaranteed by design. May not be 100% tested.
2. See Figure 13, (pg. 47).
3. See Figure 14, (pg. 48)
4. Outputs precharged to V
CC5
maximum.
Table 24. Fast Page Mode Non-interleaved DRAM Output Timings
Symbol
Description
Min
Max
Units
Notes
T
OV6
RAS3:0# Rising and Falling edge Output Valid
Delay
1
9
ns
2
T
OV7
CAS7:0# Rising Edge Output Valid Delay
1
8
ns
2
T
OV8
CAS7:0# Falling Edge Output Valid Delay
0.5Tc+1
0.5Tc+8
ns
1,2
T
OV9
MA11:0 Output Valid Delay-Row Address
0.5Tc+1
0.5Tc+10
ns
1,2
T
OV10
MA11:0 Output Valid Delay-Column Address
1
10
ns
2
T
OV11
DWE1:0# Rising and Falling edge Output Valid
Delay
1
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK
period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.
2. Output switching between V
CC3
maximum and V
SS
.
Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 1 of 2)
Symbol
Description
Min
Max
Units
Notes
T
OV12
RAS3:0# Rising and Falling edge Output Valid
Delay
1
9
ns
2
T
OV13
CAS7:0# Rising Edge Output Valid Delay
1
8
ns
2
T
OV14
CAS7:0# Falling Edge Output Valid Delay
0.5Tc+1
0.5Tc+8
ns
1,2
T
OV15
MA11:0 Output Valid Delay-Row Address
0.5Tc+1
0.5Tc+10
ns
1,2
T
OV16
MA11:0 Output Valid Delay-Column Address
1
10
ns
2
T
OV17
DWE1:0# Rising and Falling Edge Output Valid
Delay
1
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK
period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.
2. Output switching between V
CC3
maximum and V
SS
.
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