- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377123 > i960 VH (Intel Corp.) Embedded-PCI Processor(嵌入式PCI處理器) PDF資料下載
參數(shù)資料
| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 16/64頁 |
| 文件大?。?/td> | 851K |
| 代理商： | I960 VH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
80960VH
16
Preliminary Datasheet
H (...)
While the is in the hold state, the signal:
H(1) is driven to V
CC
H(0) is driven to V
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
P (...)
While the 80960VH is halted, the signal:
P(1) is driven to V
CC
P(0) is driven to V
P(Q) Maintains previous state or continues to be a valid output
K (...)
While the PCI Bus is in park mode, the pin:
K(Z) Floats
K(Q) Maintains previous state or continues to be a valid output
Table 4. Signal Descriptions (Sheet 1 of 4)
NAME
TYPE
DESCRIPTION
AD31:0
I/O
S(L)
R(Z)
H(Z)
P(Q)
ADDRESS / DATA BUS
carries 32-bit physical addresses and 8-, 16- or 32-
bit data to and from memory. During an address (
T
) cycle, bits 2-31 contain a
physical word address (bits 0-1 indicate SIZE; see below). During a data (T
d
)
cycle, read or write data is present on one or more contiguous bytes,
comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations,
unused signals are driven to determinate values.
SIZE
, which comprises bits 0-1 of the AD lines during a
T
cycle, specifies the
number of data transfers during the bus transaction on the local bus.
When the DMA or ATUs initiate data transfers, transfer size shown below is
not
valid.
AD1
AD0
0
0
0
1
1
0
1
1
When the 80960VH enters Halt mode and the previous bus operation was:
write — AD31:2 are driven with the last data value on the AD bus.
read — AD31:2 are driven with the last address value on the AD bus.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
Bus Transfers
1 Transfer
2 Transfers
3 Transfers
4 Transfers
ADS#
O
R(1)
H(Z)
P(1)
ADDRESS STROBE
indicates a valid address and the start of a new bus
access. The processor asserts ADS# for the entire
T
cycle. External bus
control logic typically samples ADS# at the end of the cycle.
ALE
O
R(0)
H(Z)
P(0)
ADDRESS LATCH ENABLE
indicates the transfer of a physical address.
ALE is asserted during a
T
cycle and deasserted before the beginning of the
T
d
state. It is active HIGH and floats to a high impedance state during a hold
cycle (T
h
).
BURST LAST
indicates the last transfer in a bus access. BLAST# is asserted
in the last data transfer of burst and non-burst accesses. BLAST# remains
active while wait states are detected via the LRDYRCV# or RDYRCV# signal
on the memory controller. BLAST# becomes inactive after the final data
transfer in a bus cycle. BLAST# has a weak internal pullup which is active
during reset to ensure normal operation when the signal is not connected.
0 = Last Data Transfer
1 = Not the Last Data Transfer
BLAST#
O
R(H)
H(Z)
P(1)
Table 3. Signal Type Definition
Symbol
Description
相關PDF資料 |
PDF描述 |
|---|---|
| ICS524 | LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS524MILF | LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS524MILFT | LOW SKEW 1 TO 4 CLOCK BUFFER |
| ICS548A-03 | LOW SKEW CLOCK INVERTER AND DIVIDER |
| ICS548AM-03LF | LOW SKEW CLOCK INVERTER AND DIVIDER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| I9906A | 功能描述:SOLENOID OPEN 3/4" CONT 24VDC RoHS:是 類別:電機，螺線管 >> 螺線管 系列:L-28 標準包裝:1 系列:* 其它名稱:Q7010103 |
| IA.32PMETAMKSD12 | 制造商:Banner Engineering 功能描述:FIBER IA.32PMETAMKSD12 NOTE: BOX CONTAIN PR OF FIBERS |
| IA.7512PMTA | 制造商:Banner Engineering 功能描述:Fiber Optic, Glass, Sensor Probe, 90 Degree Angle, 24630 |
| IA.753SMETA | 制造商:Banner Engineering 功能描述:FIBER IA.753SMETA |
| IA.753SMTA | 制造商:Banner Engineering 功能描述:FIBER IA.753SMTA ;ROHS COMPLIANT: YES |
發(fā)布緊急采購，3分鐘左右您將得到回復。