參數(shù)資料
型號(hào): i960 VH
廠商: Intel Corp.
英文描述: Embedded-PCI Processor(嵌入式PCI處理器)
中文描述: 嵌入式PCI處理器(嵌入式處理器的PCI)
文件頁數(shù): 44/64頁
文件大?。?/td> 851K
代理商: I960 VH
80960VH
44
Preliminary Datasheet
4.4.3
Boundary Scan Test Signal Timings
T
OV43
MA11:0 Output Valid Delay - Initial Address
0.5Tc+1
0.5Tc +10
ns
2
T
OV44
MA11:0 Output Valid Delay - Burst Address
1
10
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK
period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.
2. Output switching between V
CC3
maximum and V
SS
.
Table 27. SRAM/ROM Output Timings (Sheet 2 of 2)
Symbol
Description
Min
Max
Units
Notes
Table 28. Boundary Scan Test Signal Timings
Symbol
Parameter
Min
Max
Units
Notes
T
BSF
TCK Frequency
0
0.5T
F
MHz
T
BSCH
TCK High Time
15
ns
Measured at 1.5 V (1)
T
BSCL
TCK Low Time
15
ns
Measured at 1.5 V (1)
T
BSCR
TCK Rise Time
5
ns
0.8 V to 2.0 V (1)
T
BSCF
TCK Fall Time
5
ns
2.0 V to 0.8 V (1)
T
BSIS1
Input Setup to TCK
— TDI,
TMS
4
ns
T
BSIH1
Input Hold from TCK — TDI,
TMS
6
ns
(1)
T
BSOV1
TDO Valid Delay
3
30
ns
Relative to falling edge of TCK (1,2)
T
BSOF1
TDO Float Delay
3
30
ns
Relative to falling edge of TCK (1,2)
T
BSOV2
All Outputs (Non-Test) Valid
Delay
3
30
ns
Relative to falling edge of TCK (1,2)
T
BSOF2
All Outputs (Non-Test) Float
Delay
3
30
ns
Relative to falling edge of TCK (1,2)
T
BSIS2
Input Setup to TCK — All
Inputs (Non-Test)
4
ns
(1)
T
BSIH2
Input Hold from TCK — All
Inputs (Non-Test)
6
ns
(1)
NOTES:
1. Guaranteed by design. Not tested.
2. Outputs precharged to V
CC5
maximum.
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