參數(shù)資料
型號： i960 VH
廠商： Intel Corp.
英文描述： Embedded-PCI Processor(嵌入式PCI處理器)
中文描述： 嵌入式PCI處理器（嵌入式處理器的PCI）
文件頁數(shù)： 43/64頁
文件大?。?/td> 851K
代理商： I960 VH
80960VH
Preliminary
Datasheet
43
T
OV18
DALE1:0 Initial Falling Edge Output Valid Delay
1
10
ns
2
T
OV19
DALE1:0 Burst Falling Edge Output Valid Delay
0.5Tc+1
0.5Tc+10
ns
1,2
T
OV20
DALE1:0 Rising Edge Output Valid Delay
1
10
ns
2
T
OV21
LEAF1:0# Rising and Falling Edge Output Valid
Delay
1
10
ns
2
Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet 2 of 2)
Symbol
Description
Min
Max
Units
Notes
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK
period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.
2. Output switching between V
CC3
maximum and V
SS
.
Table 26. EDO DRAM Output Timings
Symbol
Description
Min
Max
Units
Note
s
T
OV22
RAS3:0# Rising and Falling Edge Output Valid Delay
1
9
ns
2
T
OV23
CAS7:0# Rising Edge Output Valid Delay -
Read Cycles
0.5Tc+1
0.5Tc+8
ns
1,2
T
OV24
CAS7:0# Falling Edge Output Valid Delay -
Read Cycles
1
8
ns
2
T
OV25
CAS7:0# Rising Edge Output Valid Delay -
Write Cycles
1
8
ns
2
T
OV26
CAS7:0# Falling Edge Output Valid Delay -
Write Cycles
0.5Tc+1
0.5Tc+8
ns
1,2
T
OV27
MA11:0 Output Valid Delay - Row Address
0.5Tc+1
0.5Tc+10
ns
1,2
T
OV28
MA11:0 Output Valid Delay - Column Address Read Cycles
0.5Tc+1
0.5Tc+10
ns
1,2
T
OV29
MA11:0 Output Valid Delay - Column Address Write Cycles
1
10
ns
2
T
OV30
DWE1:0# Rising and Falling Edge Output Valid Delay
1
11
ns
2
NOTES:
1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an P_CLK
period. For testing purposes, the signal is specified relative to the rising edge of P_CLK with the 0.5Tc period offset.
2. Output switching between V
CC3
maximum and V
SS
.
Table 27. SRAM/ROM Output Timings (Sheet 1 of 2)
Symbol
Description
Min
Max
Units
Notes
T
OV40
CE1:0# Rising and Falling Edge Output Valid
Delay
1
8
ns
2
T
OV41
MWE3:0# Rising Edge Output Valid Delay
1
9
ns
2
T
OV42
MWE3:0# Falling Edge Output Valid Delay
0.5Tc+1
0.5Tc +9
ns
1,2
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