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參數(shù)資料
| 型號： | i960 VH |
| 廠商： | Intel Corp. |
| 英文描述： | Embedded-PCI Processor(嵌入式PCI處理器) |
| 中文描述： | 嵌入式PCI處理器（嵌入式處理器的PCI） |
| 文件頁數(shù)： | 17/64頁 |
| 文件大?。?/td> | 851K |
| 代理商： | I960 VH |
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80960VH
Preliminary
Datasheet
17
BE3:0#
O
R(1)
H(Z)
P(1)
BYTE ENABLES
select which of up to four data bytes on the bus participate
in the current bus access. Byte enable encoding depends on the bus width of
the memory region accessed:
32-bit bus:
BE3# enables data on AD31:24
BE2# enables data on AD23:16
BE1# enables data on AD15:8
BE0# enables data on AD7:0
16-bit bus:
BE3# becomes Byte High Enable (enables data on AD15:8)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Byte Low Enable (enables data on AD7:0)
8-bit bus:
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Address Bit 0 (A0)
(increments with the assertion of LRDY# or RDYRCV#)
The processor asserts byte enables, byte high enable and byte low enable
during
T
. Since unaligned bus requests are split into separate bus
transactions, these signals do not toggle during a burst (32-bit bus only) from
the i960 core processor; they do toggle for DMA and ATU cycles. They remain
active through the last T
d
cycle.
DEN#
O
R(H)
H(Z)
P(1)
DATA ENABLE
indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at
the end of the last data cycle. DEN# is used with DT/R# to provide control for
data transceivers connected to the data bus. DEN# has a weak internal pullup
which is active during reset to ensure normal operation when the signal is not
connected.
0 = Data Cycle
1 = Not a Data Cycle
D/C#
/
RST_MODE#
I/O
R(H)
H(Z)
P(Q)
DATA/CODE/RESET_MODE
indicates that a bus access is a data access or
an instruction access. D/C# has the same timing as W/R#.
0 = Instruction Access
1 = Data Access
The RST_MODE# signal is sampled at primary PCI bus reset to determine
whether the 80960 core is to be held in reset. When RST_MODE# is high, the
80960VH begins initialization immediately following the deassertion of
P_RST#. When RST_MODE# is low, the 80960 core remains in reset until the
80960 core reset bit is cleared in the Reset/Retry control register. This signal
has a weak internal pullup that is active during reset to ensure normal
operation when the signal is left unconnected.
0 = RST_MODE enabled
1 = RST_MODE not enabled
While the 80960 core is in reset, all peripherals may be accessed from the
primary PCI bus depending on the status of the WIDTH/HLTD1/RETRY/
signal.
DT/R#
O
R(0)
H(Z)
P(Q)
DATA TRANSMIT/RECEIVE
indicates the direction of data transfer to and
from the address/data bus. It is low during T
and T
/T
d
cycles for a read; it is
high during
T
and T
w
/T
d
cycles for a write. DT/R# never changes state when
DEN# is asserted.
0 = Receive
1 = Transmit
Table 4. Signal Descriptions (Sheet 2 of 4)
NAME
TYPE
DESCRIPTION
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