參數(shù)資料
型號(hào): i960 VH
廠商: Intel Corp.
英文描述: Embedded-PCI Processor(嵌入式PCI處理器)
中文描述: 嵌入式PCI處理器(嵌入式處理器的PCI)
文件頁數(shù): 40/64頁
文件大?。?/td> 851K
代理商: I960 VH
80960VH
40
Preliminary Datasheet
4.4
AC Specifications
Table 20. Input Clock Timings
Symbol
Parameter
Min
Max
Units
Notes
T
F
P_CLK Frequency
16
33.33
MHz
T
C
P_CLK Period
30
62.5
ns
(1)
T
CS
P_CLK Period Stability
±250
ps
Adjacent Clocks (2,3)
T
CH
P_CLK High Time
12
ns
Measured at 1.5 V (2,3)
T
CL
P_CLK Low Time
12
ns
Measured at 1.5 V (2,3)
T
CR
P_CLK Rise Time
4
V/ns
0.4 V to 2.4 V (2,3)
T
CF
P_CLK Fall Time
4
V/ns
2.4 V to 0.4 V (2,3)
NOTES:
1. See Figure 9, (pg. 46).
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum
should not have any power peaking between 500 KHz and 1/3 of the P_CLK frequency.
3. Not tested.
Table 21. Synchronous Output Timings
Symbol
Parameter
Min
Max
Units
Notes
T
OV1
Output Valid Delay - All Local Bus Signals Except
ALE Inactive and DT/R#
2
15.5
ns
(1,2,5)
T
OV2
Output Valid Delay, DT/R#
0.5 T
C
+3
0.5 T
C
+15
ns
(2,5)
T
OV3
Output Valid Delay - PCI Signals Except P_REQ#
2
11
ns
(2,5)
T
OV4
Output Valid Delay P_REQ#
2
12
ns
(2,5)
T
OV5
Output Valid Delay - DP3:0
3
19
ns
(2,5)
T
OF
Output Float Delay
3
13
ns
(3,4,5)
NOTES:
1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see
Table 23, Relative Output Timings (pg. 42)
.
2. See Figure 10, (pg. 46).
3. A float condition occurs when the output current becomes less than I
LO
. Float delay is not tested, but is designed to be no
longer than the valid delay.
4. See Figure 11, (pg. 47).
5. Outputs precharged to V
CC5
maximum.
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